Semiconductor package integrating active and passive components with electromagnetic shielding

1. A semiconductor package comprising:

a support member including a resin body having a first surface and a second surface opposing each other and having a cavity passing through the first surface and the second surface, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface;

a first connection member having a first insulating layer disposed on the first surface of the resin body, and a first redistribution layer disposed on the first insulating layer and connected to the connection terminal;

a second connection member having a second insulating layer disposed on the first connection member and covering a surface of the cavity, and a second redistribution layer disposed on the second insulating layer and connected to the first redistribution layer;

a semiconductor chip disposed on the second connection member in the cavity and having a connection pad connected to the second redistribution layer; and

an encapsulant covering the second surface of the resin body while encapsulating the semiconductor chip located in the cavity,

wherein a plane extending from the first surface of the resin body intersects a side surface of the semiconductor chip, and

wherein a thickness of the first connection member corresponds to a first distance from the plane to a surface of the semiconductor chip on which the connection pad is disposed.

2. The semiconductor package of claim 1 , further comprising a first shielding layer disposed on the second surface of the resin body and an inner side wall of the cavity, and connected to the first redistribution layer,

wherein the first shielding layer extends along an entire width of the second surface of the resin body.

3. The semiconductor package of claim 2 , further comprising a second shielding layer disposed on an upper surface of the encapsulant, and connected to the first shielding layer.

4. The semiconductor package of claim 3 , wherein the second shielding layer extends along a side surface of the resin body, and is connected to the first shielding layer on the side surface of the resin body.

5. The semiconductor package of claim 3 , wherein the second shielding layer is connected to the first shielding layer by a metal trench passing through the encapsulant.

6. The semiconductor package of claim 3 , further comprising a heat sink disposed on an upper surface of the semiconductor chip,

wherein the heat sink is connected to the second shielding layer by a metal via passing through the encapsulant.

7. The semiconductor package of claim 1 , wherein a lower surface of the first connection member is substantially coplanar with the surface on which the connection pad of the semiconductor chip is disposed.

8. The semiconductor package of claim 1 , wherein the first insulating layer and the second insulating layer include different insulating materials.

9. The semiconductor package of claim 8 , wherein the first insulating layer includes a non-photo imagable dielectric material, and the second insulating layer includes a photo imagable dielectric material.

10. The semiconductor package of claim 1 , wherein the second connection member comprises a third redistribution layer disposed on a level different from a level of the second redistribution layer in the second insulating layer and connected to the second redistribution layer.

11. The semiconductor package of claim 10 , wherein the second connection member further comprises a trench stack disposed along an edge of the second connection member.

12. The semiconductor package of claim 11 , further comprising a first shielding layer disposed on the second surface of the resin body and an inner side wall of the cavity, and connected to the first redistribution layer, and

a second shielding layer disposed on an upper surface of the encapsulant, and extending along a side surface of the resin body and connected to the first shielding layer and the trench stack.

13. The semiconductor package of claim 1 , further comprising a passivation layer disposed on a lower surface of the second connection member, and having a plurality of openings exposing a portion of the second redistribution layer, and

an electrical connection structure disposed in the plurality of openings of the passivation layer, and connected to the exposed portion of the second redistribution layer.

14. A semiconductor package comprising:

a support member including a resin body having a first surface and a second surface opposing each other and having at least one cavity passing through the first surface and the second surface, and a plurality of passive components embedded in the resin body and having a connection terminal exposed from the first surface;

a first connection member having a first insulating layer disposed on the first surface of the resin body, and a first redistribution layer disposed on the first insulating layer and connected to the connection terminal;

a second connection member having a second insulating layer disposed on a lower surface of the first connection member and covering a surface of the at least one cavity, and second redistribution layers disposed on different levels in the second insulating layer, the second redistribution layers being connected to the first redistribution layer or another adjacent second redistribution layer;

a first semiconductor chip disposed on the second connection member in the at least one cavity and having a connection pad connected to the second redistribution layers;

a first shielding layer disposed on the second surface of the resin body and an inner side wall of the at least one cavity, and connected to the first redistribution layer;

an encapsulant covering the second surface of the resin body while encapsulating the first semiconductor chip located in the at least one cavity; and

a second shielding layer disposed on an upper surface of the encapsulant, and connected to the first shielding layer,

wherein a plane extending from the first surface of the resin body intersects a side surface of the first semiconductor chip, and

wherein a thickness of the first connection member corresponds to a first distance from the plane to a surface of the first semiconductor chip on which the connection pad is disposed.

15. The semiconductor package of claim 14 , wherein the at least one cavity includes a plurality of cavities, in which the first semiconductor chip and second semiconductor chips disposed, respectively, and the first shielding layer extends along an inner side wall of each of the plurality of cavities.

16. A semiconductor package comprising:

a resin body having a first surface and a second surface opposing each other, and a passive component partially embedded in the resin body and having a connection terminal exposed from the resin body;

a first connection member including a first insulating layer disposed on the resin body, and a first redistribution layer disposed on the first insulating layer and including a first redistribution via penetrating the first insulating layer and connected to the connection terminal of the passive component;

a semiconductor chip disposed in a cavity of the resin body and having a connection pad;

a second connection member having a second insulating layer disposed on the first connection member and the semiconductor chip, and a second redistribution layer disposed on the second insulating layer and connected to the first redistribution layer and the connection pad of the semiconductor chip; and

an encapsulant covering the resin body and the semiconductor chip, and including a portion disposed between the semiconductor chip and the first insulating layer of the first connection member,

wherein a plane extending from the first surface of the resin body intersects a side surface of the semiconductor chip, and

wherein a thickness of the first connection member corresponds to a first distance from the plane to a surface of the semiconductor chip on which the connection pad is disposed.

17. The semiconductor package of claim 16 , further comprising a first shielding layer disposed on the resin body and an inner side wall of the cavity, connected to the first redistribution layer, and separating the portion of the encapsulant from the first insulating layer,

wherein the first shielding layer extends along an entire width of the second surface of the resin body.

18. The semiconductor package of claim 17 , further comprising a second shielding layer disposed on the encapsulant and connected to the first shielding layer.

19. The semiconductor package of claim 18 , wherein the second shielding layer extends along a side surface of the resin body, and is connected to the first shielding layer on the side surface of the resin body.

20. The semiconductor package of claim 19 , wherein the second connection member further comprises a trench stack disposed along an edge of the second connection member, and

the second shielding layer further extends to cover a side surface of the second connection member and to connect to the trench stack on the side surface of the second connection member.

21. The semiconductor package of claim 18 , wherein the second shielding layer is connected to the first shielding layer by a metal trench passing through the encapsulant.

22. The semiconductor package of claim 18 , further comprising a heat sink disposed on the semiconductor chip,

wherein the heat sink is connected to the second shielding layer by a metal via passing through the encapsulant.

23. The semiconductor package of claim 16 , wherein lower surfaces of the first connection member and the connection pad of the semiconductor chip are substantially coplanar with each other.

24. A semiconductor package comprising:

a resin body having a first surface and a second surface opposing each other, and a passive component partially embedded in the resin body and having a connection terminal exposed from the resin body;

a semiconductor chip disposed in a cavity of the resin body and having a connection pad;

a connection member having an insulating layer disposed on the resin body and the semiconductor chip, and a redistribution layer disposed on the insulating layer and connected to the connection terminal of the passive component and the connection pad of the semiconductor chip;

an encapsulant covering the resin body and the semiconductor chip, and including a portion disposed between the semiconductor chip and the resin body; and

a first shielding layer including a first portion disposed on an upper surface of the resin body and a second portion extending from the first portion and covering an inner side wall of the cavity,

wherein the second portion covering the inner side wall of the cavity is in physical contact with a portion of the resin body between the passive component and the semiconductor chip, and

wherein a plane extending from the first surface of the resin body intersects a side surface of the semiconductor chip, and

wherein a thickness of the connection member corresponds to a first distance from the plane to a surface of the semiconductor chip on which the connection pad is disposed.

25. The semiconductor package of claim 24 , further comprising a second shielding layer disposed on the encapsulant and connected to the first shielding layer.

26. The semiconductor package of claim 25 , wherein the second shielding layer includes a portion extends along a side surface of the resin body, and

the portion of the second shielding layer is in physical contact with a portion of the resin body between the passive component and the portion of the second shielding layer.

27. The semiconductor package of claim 24 , wherein the first shielding layer extends along an entire width of the second surface of the resin body.