IP Library Granted Patent US 11,694,976
Granted Patent B2
US 11,694,976 · App. 16/158,042 · Granted Jul 4, 2023

Bowl shaped pad

Inventors: Yuhong Cai (Folsom, CA); Sireesha Gogineni (Folsom, CA); Yi Xu (Folsom, CA)
Assignee: Intel Corporation
H01L24/05H01L24/03H01L24/13H01L2224/03612H01L2224/0401H01L2224/05011H01L2224/13026
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Quick Facts
Patent No.
US 11,694,976
App. No.
16/158,042
Granted
Jul 4, 2023
Kind
B2
Abstract

Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.

Claims (26)

1. An interconnect structure, comprising:

a substrate; and

a metal pad over the substrate, wherein the metal pad has a center region and an edge region, wherein a thickness of the center region is smaller than a thickness of the edge region, wherein a thickness of the center region is non-uniform, wherein the center region is characterized by a stepped profile, wherein the stepped profile is formed from steps, and wherein each step comprises a horizontal surface and a vertical surface.

2. The interconnect structure of claim 1 , wherein the substrate is a printed circuit board.

3. The interconnect structure of claim 1 , wherein the substrate is a semiconductor package.

4. The interconnect structure of claim 1 , further comprising an interconnect joint on the metal pad.

5. An interconnect structure, comprising:

a first substrate;

a metal pad over the first substrate, wherein the metal pad has a center region and an edge region, wherein a thickness of the center region is smaller than a thickness of the edge region, wherein a thickness of the center region is non-uniform wherein the center region comprises steps having non-uniform thicknesses;

a second substrate over the metal pad; and

solder disposed in or on the metal pad, the solder coupling the first and second substrates to each other.

6. An interconnect structure, comprising:

a substrate; and

a metal pad over the substrate, wherein the metal pad has a center region and an edge region, wherein a thickness of the center region is smaller than a thickness of the edge region, wherein a pattern is formed in a surface of the metal pad, and wherein the pattern comprises one or more polygons.

7. The interconnect structure of claim 6 , wherein the substrate is a printed circuit board.

8. The interconnect structure of claim 6 , wherein the substrate is a semiconductor package.

9. The interconnect structure of claim 6 , further comprising an interconnect joint on the metal pad.

10. An interconnect structure, comprising:

a substrate; and

a metal pad over the substrate, wherein the metal pad has a center region and an edge region, wherein a thickness of the center region is smaller than a thickness of the edge region, wherein a pattern is formed in a surface of the metal pad, and wherein the pattern comprises a line segment.

11. The interconnect structure of claim 10 , wherein the line segment extends from the center region to the edge region.

12. The interconnect structure of claim 10 , wherein the line segment is a straight line segment.

13. The interconnect structure of claim 10 , wherein the line segment is a curved line segment.

14. The interconnect structure of claim 10 , wherein the substrate is a printed circuit board.

15. The interconnect structure of claim 10 , wherein the substrate is a semiconductor package.

16. The interconnect structure of claim 10 , further comprising an interconnect joint on the metal pad.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072850/0834 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2019
From: CAI, YUHONG; GOGINENI, SIREESHA; XU, YI
To: INTEL CORPORATION
Reel/Frame 048256/0975 →
Continuity (1)
Related Publication 20200118954A1 · Apr 16, 2020