PMOS-output LDO with full spectrum PSR
A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (M O ) having a source coupled to an input voltage (Vin); a noise cancelling transistor (M D ) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (M SF ) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.
1. A low dropout (LDO) regulator circuit, comprising:
a pass transistor (M O ) having a source, a drain, and a gate, the source coupled to an input voltage (Vin);
a noise cancelling transistor (M D ) having a source, a drain, and a gate, the source coupled to the Vin, the gate coupled to the drain of the noise cancelling transistor and the gate of the pass transistor;
a source follower transistor (M SF ) having a source, a drain, and a gate, the source coupled to the drain of the pass transistor, the drain coupled to the drain and the gate of the noise cancelling transistor;
a current sink coupled between the drain of the source follower transistor and ground;
an error amplifier having an output, a positive input terminal, and a negative input terminal, the output coupled to the gate of the source follower transistor, the positive input terminal configured to receive a reference voltage (Vref); and
a feedback resistor coupled between the drain of the pass transistor and the negative input terminal of the error amplifier.
2. The LDO regulator circuit of claim 1 , further comprising:
a load capacitor coupled between the drain of the pass transistor and ground.
3. The LDO regulator circuit of claim 2 , wherein the load capacitor has a capacitance of 2 pF.
4. The LDO regulator circuit of claim 1 , wherein the source follower transistor, the feedback resistor, and the error amplifier are configured into a first loop.
5. The LDO regulator circuit of claim 4 , wherein the pass transistor, the noise canceling transistor, and the source follower transistor are configured into a second loop.
6. The LDO regulator circuit of claim 5 , wherein the first loop is configured to be a slow loop and the second loop is configured to be a fast loop.
7. The LDO regulator circuit of claim 1 , wherein the error amplifier comprises a pair of p-type transistors configured as a current mirror, and sources of the pair of p-type transistors are coupled to the Vin.
8. The LDO regulator circuit of claim 7 , wherein the error amplifier further comprises a first n-type transistor configured as the positive input terminal and a second n-type transistor configured as the negative input terminal.
9. A method to provide a regulated low voltage from an input voltage (Vin), the method comprising:
receiving the input voltage at a source of a pass transistor (M O );
coupling a source of a noise cancelling transistor (M D ) to the source of the pass transistor, wherein the noise cancelling transistor is configured into a diode;
coupling a source of a source follower transistor (M SF ) to a drain of the pass transistor, and coupling a drain of the source follower transistor to a drain and a gate of the noise cancelling transistor;
coupling a current sink between the drain of the source follower transistor and ground;
receiving a reference voltage (Vref) at a positive input terminal of an error amplifier;
coupling a feedback resistor between the drain of the pass transistor and a negative input terminal of the error amplifier to provide a feedback voltage to the error amplifier;
generating an output of the error amplifier based on the feedback voltage and the reference voltage; and
driving a gate of the source follower transistor with the output of the error amplifier.
10. The method of claim 9 , further comprising:
coupling a load capacitor between the drain of the pass transistor and the ground.
11. The method of claim 10 , wherein the load capacitor has a capacitance of 2 pF.
12. The method of claim 9 , further comprising configuring the source follower transistor, the feedback resistor, and the error amplifier into a first loop.
13. The method of claim 12 , further comprising configuring the pass transistor, the noise canceling transistor, and the source follower transistor into a second loop.
14. The method of claim 13 , wherein the first loop is a slow loop and the second loop is a fast loop.
15. The method of claim 9 , wherein the error amplifier comprises a pair of p-type transistors configured as a current mirror, and sources of the pair of p-type transistors are coupled to Vin.
16. The method of claim 15 , wherein the error amplifier further comprises a first n-type transistor configured as the positive input terminal and a second n-type transistor configured as the negative input terminal.