Low drop-out circuit, electronic device, and method of manufacturing the same

1. A low dropout (LDO) circuit, comprising:

an input terminal;

an output terminal;

a cascode operational amplifier electrically connected to the input terminal; and

a power stage having a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal,

wherein the power stage comprises:

a first transistor having a source electrically connected to the input terminal and a gate electrically connected to the output node of the cascode operational amplifier; and

a second transistor having a source electrically connected to a drain of the first transistor of the power stage, a gate configured to receive an adaptive bias voltage, and a drain electrically connected to the output terminal.

2. The LDO circuit of claim 1 , wherein the cascode operational amplifier comprises:

a first transistor having a gate configured to receive a feedback voltage, wherein the feedback voltage is smaller than a voltage at the output terminal;

a second transistor having a gate configured to receive a reference voltage;

wherein a source of the first transistor of the cascode operational amplifier and a source of the second transistor of the cascode operational amplifier are electrically connected with each other.

3. The LDO circuit of claim 2 , wherein the cascode operational amplifier further comprises:

a third transistor having a source electrically connected to the input terminal and a drain electrically connected to a drain of the first transistor of the cascode operational amplifier;

a fourth transistor having a source electrically connected to the input terminal and a drain electrically connected to a drain of the second transistor of the cascode operational amplifier,

wherein a gate of the third transistor and a gate of the fourth transistor are electrically connected with each other.

4. The LDO circuit of claim 3 , wherein the cascode operational amplifier further comprises:

a first switch transistor having a source electrically connected to the gate of the third transistor, a drain electrically connected to the drain of the third transistor, and a gate configured to receive a first bias voltage,

wherein the first bias voltage is smaller than a voltage at the input terminal.

5. The LDO circuit of claim 4 , wherein the cascode operational amplifier further comprises:

a fifth transistor having a source electrically connected to the drain of the third transistor;

a sixth transistor having a source electrically connected to the drain of the fourth transistor;

a seventh transistor having a source electrically connected to the drain of the first transistor of the cascode operational amplifier and a drain electrically connected to the drain of the fifth transistor;

an eighth transistor having a source electrically connected to the drain of the second transistor of the cascode operational amplifier and a drain electrically connected to the drain of the sixth transistor,

wherein a gate of the fifth transistor and a gate of the sixth transistor are electrically connected with each other and configured to receive a second bias voltage, and

wherein and a gate of the seventh transistor and a gate of the eighth transistor are electrically connected with each other and configured to receive a third bias voltage.

6. The LDO circuit of claim 5 , wherein the third bias voltage is smaller than the second bias voltage, and the second bias voltage is smaller than the first bias voltage.

7. The LDO circuit of claim 5 , wherein the cascode operational amplifier further comprises:

a second switch transistor having a source electrically connected to the gate of the sixth transistor, a drain electrically connected to the drain of the sixth transistor, and a gate configured to receive a fourth bias voltage,

wherein the fourth bias voltage is smaller than the voltage at the input terminal.

8. The LDO circuit of claim 7 , wherein the cascode operational amplifier further comprises:

a third switch transistor having a drain electrically connected to the gate of the seventh transistor, a source electrically connected to the drain of the seventh transistor, and a gate configured to receive a first power control signal.

9. The LDO circuit of claim 8 , wherein:

the LDO circuit is configured to operate in a first mode when the first switch transistor is turned on and the second and third switch transistors are turned off,

the LDO circuit is configured to operate in a second mode when the first switch transistor is turned off and the second and third switch transistors are turned on, and

wherein the second mode indicates that the LDO circuit is disabled.

10. The LDO circuit of claim 8 , wherein the cascode operational amplifier further comprises a fourth switch transistor having a source electrically connected to the drain of the sixth transistor, a drain electrically connected to the second terminal of the power stage, and a gate configured to receive a power control signal.

11. The LDO circuit of claim 10 , wherein:

the LDO circuit operates in a first mode when the fourth switch transistor is turned on,

the LDO circuit is configured to operate in a second mode when the fourth switch transistor is turned off, and wherein the second mode indicates that the LDO circuit is disabled.

12. The LDO circuit of claim 1 , further comprising a compensation circuit electrically connected between the gate of the first transistor of the power stage and the drain of the second transistor of the power stage, wherein the compensation circuit provides a zero for a frequency response of the LDO circuit.

13. The LDO circuit of claim 1 , further comprising a feedback circuit, wherein the feedback circuit has a first terminal electrically connected to the output terminal and a second terminal configured to provide a feedback voltage to the cascode operational amplifier.

14. The LDO circuit of claim 1 , wherein the power stage has a rectangular area on a substrate in which the LDO circuit is disposed.

15. An electronic device, comprising:

an input terminal;

an output terminal;

an amplifier electrically connected to the input terminal; and

a power stage having a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the amplifier, and a third terminal electrically connected to the output terminal,

wherein the amplifier comprises a fourth switch transistor electrically connected to the third terminal of the power stage, and

wherein:

the electronic device is configured to operate in a first mode when the fourth switch transistor is turned on,

the electronic device is configured to operate in a second mode when the fourth switch transistor is turned off, and

wherein the second mode indicates that the electronic device is disabled.

16. The electronic device of claim 15 , further comprising a compensation circuit electrically connected between the fourth switch transistor and the output terminal, wherein the compensation circuit provides a zero for a frequency response of the LDO circuit.

17. The electronic device of claim 15 , wherein the amplifier is a cascode operational amplifier, comprising:

a fifth transistor;

a sixth transistor having a gate electrically connected with a gate of the fifth transistor;

a seventh transistor having a drain electrically connected to the drain of the fifth transistor; and

an eighth transistor having a drain electrically connected to the drain of the sixth transistor, and a gate electrically connected to a gate of the seventh transistor.

18. A method of manufacturing a low dropout (LDO) circuit, comprising:

providing a substrate;

forming a first transistor and a second transistor of a power stage in a series connection in the substrate;

wherein the first transistor has a source electrically connected to an input terminal of the LDO circuit and a gate electrically connected to an output node of a cascode operational amplifier of the LDO circuit;

wherein the second transistor has a source electrically connected to a drain of the first transistor, a gate configured to receive an adaptive bias voltage, and a drain electrically connected to an output terminal of the LDO circuit.

19. The method of claim 18 , further comprising:

forming a first via stacking structure electrically connected to the first transistor of the power stage; and

forming a second via stacking structure electrically connected to the second transistor of the power stage.

20. The method of claim 19 , further comprising:

forming a first conductive layer electrically connecting the first via stacking structure and the input terminal of the LDO circuit; and

forming a second conductive layer electrically connecting the second via stacking structure and the output terminal of the LDO circuit,

wherein the second conductive layer extends in a direction perpendicular to the extending direction of the second via stacking structure.