Electronic device including a low dropout (LDO) regulator

1. An electronic device, comprising:

a voltage generator having an input and an output; and

a low drop-out (LDO) circuit having an input electrically connected to the output of the voltage generator,

wherein the voltage generator includes a first voltage regulator having a first terminal and a second terminal, wherein the first terminal of the first voltage regulator is electrically connected to the output of the voltage generator,

wherein the first voltage regulator includes a stack of a plurality of transistors.

2. The electronic device of claim 1 , wherein the input of the voltage generator is configured to receive a first voltage and the input of the LDO circuit is configured to receive a second voltage from the output of the voltage generator, wherein the first voltage exceeds the second voltage.

3. The electronic device of claim 2 , wherein the LDO circuit has a first output, and includes a transistor having a gate configured to receive a voltage signal associated with the second voltage, a source electrically connected to a supply voltage, and a drain electrically connected to the first output of the LDO circuit.

4. The electronic device of claim 3 , wherein the drain of the transistor of the LDO circuit is directly connected to an external system.

5. The electronic device of claim 3 , wherein the LDO circuit includes a feedback circuit electrically connected to the drain of the transistor of the LDO circuit.

6. The electronic device of claim 5 , wherein the feedback circuit generates a zero for a frequency response of the LDO circuit.

7. The electronic device of claim 5 , wherein the feedback circuit includes a resistor having a first terminal and a capacitor having a first terminal connected to the drain of the transistor of the LDO circuit and a second terminal connected to the first terminal of the resistor.

8. The electronic device of claim 5 , wherein the LDO includes a second OTA having a first input terminal electrically connected to the input of the LDO circuit, a second input terminal electrically connected to the feedback circuit, and an output terminal electrically connected to the gate of the transistor of the LDO circuit.

9. The electronic device of claim 8 , wherein the second OTA includes a current buffer electrically connected to the output terminal of the second OTA, such that the second OTA has lower dominant pole in a frequency response.

10. The electronic device of claim 1 , wherein the plurality of transistors include short-channel transistors.

11. The electronic device of claim 1 , wherein the voltage generator includes a second voltage regulator having a first terminal electrically connected to the second terminal of the first voltage regulator and a second terminal electrically connected to the ground.

12. The electronic device of claim 11 , wherein the voltage generator includes a first operational transconductance amplifier (OTA) having a first input terminal electrically connected to the input of the voltage generator, a second input terminal electrically connected to the second terminal of the first voltage regulator, and an output terminal electrically connected to the output of the voltage generator.

13. The electronic device of claim 12 , wherein the voltage generator includes a transistor having a gate electrically connected to the output terminal of the first OTA, a source electrically connected to a supply voltage, and a drain electrically connected to the first terminal of the first voltage regulator.

14. The electronic device of claim 1 , wherein the LDO circuit includes a low-pass filter electrically connected to the input of the LDO circuit.

15. The electronic device of claim 1 , wherein the plurality of transistors include FinFETs.

16. A voltage reference, comprising: a transistor having a gate, a source and a drain; an output circuit electrically connected to the drain of the transistor; and a constant transconductance bias circuit electrically connected to the transistor, wherein the output circuit is configured to provide various voltages, wherein the output circuit includes a stack of a plurality of short-channel transistors.

17. A low dropout (LDO) circuit, comprising:

a transistor having a gate, a source and a drain;

a feedback circuit electrically connected to the drain of the transistor; and

an operational transconductance amplifier (OTA) electrically connected to the gate of the transistor and the feedback circuit,

wherein the OTA includes a current buffer configured to reduce a dominant pole for a frequency response of the OTA.

18. The LDO circuit of claim 17 , wherein the feedback circuit generates a zero for a frequency response of the LDO circuit.

19. The LDO circuit of claim 17 , wherein the current buffer is electrically connected to an output terminal of the OTA.