IP Library Granted Patent US 11,264,423
Granted Patent B2
US 11,264,423 · App. 16/178,454 · Granted Mar 1, 2022

Solid-state imaging device having improved light-collection, method of manufacturing the same, and electronic apparatus

Inventors: Kazufumi Watanabe (Tokyo, JP); Yasushi Maruyama (Kanagawa, JP)
Assignee: SONY CORPORATION
H01L27/14645H01L27/1463H01L27/1464H01L27/14612H01L27/14621H01L27/14623H01L27/14627H01L27/14629H01L27/14632H01L27/14636H01L27/14685H01L27/14687H01L31/0216H01L31/18H04N5/359H01L21/7806H01L31/02162H01L31/1804Y02P70/50
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,264,423
App. No.
16/178,454
Granted
Mar 1, 2022
Kind
B2
Abstract

A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged.

Claims (23)

1. A light detecting device, comprising:

a semiconductor substrate having a first side as a light incident side and a second side opposite to the first side;

first and second photoelectric conversion regions disposed in the substrate;

a trench disposed between the first and second photoelectric conversion regions;

a metal disposed in an area including in the trench in a cross-sectional view,

wherein the metal has a recessed portion within an upper surface of the metal, and

wherein the upper surface of the metal is provided above the first side of the semiconductor substrate and above an insulating film disposed adjacent to the first side of the semiconductor substrate, extending outside of the trench; and

a wiring layer disposed under the second side of the semiconductor substrate,

wherein the wiring layer includes a gate electrode and a plurality of interconnection layers provided beneath the gate electrode,

wherein a bottom surface of the metal extends beyond the second side of the semiconductor substrate and the gate electrode of the wiring layer such that the bottom surface of the metal is formed at a depth to reach a first layer of the interconnection layers and

wherein the metal connects to a ground potential.

2. The light detecting device according to claim 1 , further comprising:

a high dielectric material film disposed between the semiconductor substrate and the metal in the trench.

3. The light detecting device according to claim 1 , wherein the trench is disposed from the first side of the semiconductor substrate to the second side of the semiconductor substrate.

4. The light detecting device according to claim 1 , further comprising:

an insulating film disposed adjacent to the first side of the semiconductor substrate.

5. The light detecting device according to claim 4 , wherein the insulating film includes silicon oxide.

6. The light detecting device according to claim 5 , wherein the insulating film is in contact with the recessed portion.

7. The light detecting device according to claim 4 , wherein the insulating film is in contact with the recessed portion.

8. The light detecting device according to claim 1 , further comprising:

a high dielectric material film disposed above the first side of the semiconductor substrate.

9. The light detecting device according to claim 1 , wherein the recessed portion of the metal is disposed at the first side of the semiconductor substrate.

10. The light detecting device according to claim 1 , wherein the recessed portion of the metal is disposed above the semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: WATANABE, KAZUFUMI; MARUYAMA, YASUSHI
To: SONY CORPORATION
Reel/Frame 057044/0675 →
Priority Claims (2)
JP 2009-028822 · Feb 10, 2009 · national
JP 2009-148088 · Jun 22, 2009 · national
Continuity (6)
Continuation 15647093 · Jul 11, 2017
Continuation 15394241 · Dec 29, 2016
Continuation 14942691 · Nov 16, 2015
Continuation 14563036 · Dec 8, 2014
Division 12699488 · Feb 3, 2010
Related Publication 20190074318A1 · Mar 7, 2019