Memory devices and methods for fabricating the same

1. A memory device, comprising:

a substrate;

an isolation region and active regions disposed in the substrate;

pairs of word lines disposed in the substrate, wherein each of the active regions corresponds to one of the pairs of word lines, and each of the active regions has a drain region between one word line of the pairs of word lines and the isolation region and a source region between one of the pairs of word lines;

a first dielectric layer disposed on the substrate and covering the pairs of word lines, wherein the first dielectric layer has an opening exposing the isolation region and drain regions of neighboring two of the active regions; and

a pair of contacts and a dielectric portion disposed in the opening,

wherein the pair of contacts are separated from each other by the dielectric portion,

wherein each of the pair of contacts comprises a first conductive portion disposed on the substrate, a second conductive portion disposed over the first conductive portion and a lining layer disposed between the first conductive portion and the second conductive portion and on a sidewall of the opening,

wherein the second conductive portion has a sidewall that is in contact with the dielectric portion and the lining layer is not located thereon, and

wherein the second conductive portion has a corner in connection with the sidewall and a top surface of the second conductive portion, and a protection portion is disposed on the corner.

2. The memory device as claimed in claim 1 , further comprising a capacitor disposed on the pair of contacts, wherein the capacitor comprises a lower electrode layer, an upper electrode layer and a dielectric layer disposed therebetween, and the lower electrode layer is in connection with the substrate through the pair of contacts.

3. The memory device as claimed in claim 1 , wherein the pair of contacts are correspondingly disposed on the drain regions of neighboring two of the active regions.

4. The memory device as claimed in claim 1 , wherein each of the pair of contacts further comprises a silicide layer disposed between the first conductive portion and the lining layer.

5. The memory device as claimed in claim 1 , wherein a top surface of the dielectric layer, a top surface of the lining layer, the top surface of the second conductive portion and the top surface of the protection portion are coplanar.