IP Library › Granted Patent US 12,652,788
Granted Patent B2
US 12,652,788 · App. 18/473,601 · Granted Jun 9, 2026

Dynamic random access memory and method for forming the same

Inventor: Shou-Te Wang (Taichung City, TW)
Assignee: WINBOND ELECTRONICS CORP.
H10B12/0335H10B12/315H10B12/34H10B12/482H10B12/485
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Quick Facts
Patent No.
US 12,652,788
App. No.
18/473,601
Granted
Jun 9, 2026
Kind
B2
Abstract

A method for forming a DRAM includes forming a bit line contact over the active area, forming a bit line over the bit line contact, and forming a hard mask layer over the bit line. The method includes forming a semiconductor material layer over the active area and forming a metal layer over the semiconductor material layer and the hard mask layer. The method includes removing the metal layer over the hard mask layer and exposing the top surface of the hard mask layer, and the remaining portion of the metal layer is between hard mask layers. The method includes removing a portion of the hard mask layer after exposing a portion of the hard mask layer. The method includes forming a capacitor contact conductive layer over the remaining portion of the metal layer after removing the portion of the hard mask layer.

Claims (31)

1 . A method for forming a Dynamic Random Access Memory (DRAM), comprising:

forming an isolation structure surrounding an active area in a substrate;

forming a plurality of bit line contacts over the active area;

forming a plurality of bit lines each disposed over one of the bit line contacts;

forming a plurality of hard mask layers over the respective bit lines;

forming a plurality of blocking structures disposed between adjacent bit lines in an array region;

forming a semiconductor material layer between the blocking structures;

forming a separation material disposed in a separation trench formed in the semiconductor material layer, such that adjacent portions of the semiconductor material layer are electrically separated;

forming a metal layer over the semiconductor material layer and the hard mask layer;

forming a photoresist pattern over the metal layer, wherein the photoresist pattern exposes a top surface of the metal layer over the hard mask layer;

removing the metal layer exposed by the photoresist pattern, such that a top surface of the hard mask layer is exposed by a remaining portion of the metal layer and the photoresist pattern;

removing a portion of the hard mask layer exposed by the photoresist pattern, then removing the photoresist pattern; and

forming a capacitor contact conductive layer over the remaining portion of the metal layer after removing the portion of the hard mask layer.

2 . The method for forming a DRAM as claimed in claim 1 , further comprising:

etching back the semiconductor material layer to form a contact recess beside the bit line,

wherein the remaining portion of the metal layer forms a recess, and the capacitor contact conductive layer fills up the recess.

3 . The method for forming a DRAM as claimed in claim 2 , wherein a top surface of the semiconductor material layer is level with a top surface of the bit line after etching back the semiconductor material layer.

4 . The method for forming a DRAM as claimed in claim 2 , further comprising:

planarizing the capacitor contact conductive layer to expose a top surface of a remaining portion of the hard mask layer to form a capacitor contact in the contact recess.

5 . The method for forming a DRAM as claimed in claim 4 , wherein a top surface of the capacitor contact is level with a top surface of the remaining portion of the hard mask layer.

6 . The method for forming a DRAM as claimed in claim 2 , wherein after etching back the semiconductor material layer and before removing a portion of the hard mask layer, the hard mask layer has a curved top surface, and a top surface of a remaining portion of the hard mask layer is level with a top surface of the remaining portion of the metal layer.

7 . The method for forming a DRAM as claimed in claim 4 , wherein a top surface of the capacitor contact is level with the a surface of the remaining portion of the metal layer.

8 . The method for forming a DRAM as claimed in claim 1 , further comprising:

forming a silicide layer over the semiconductor material layer before forming the metal layer.

9 . The method for forming a DRAM as claimed in claim 1 , wherein a remaining portion of the hard mask layer is 80%-95% of a thickness of the hard mask layer before etching.

10 . The method for forming a DRAM as claimed in claim 1 , wherein a material of the metal layer and a material of the capacitor contact conductive layer are different.

11 . The method for forming a DRAM as claimed in claim 1 , wherein the metal layer comprises Co, and the capacitor contact conductive layer comprises W.

12 . The method for forming a DRAM as claimed in claim 1 , wherein a remaining portion of the hard mask layer has a flat top surface.

13 . The method for forming a DRAM as claimed in claim 1 , further comprising:

implanting the active area before removing the portion of the hard mask layer.

14 . The method for forming a DRAM as claimed in claim 1 , wherein the photoresist pattern covers a periphery region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2023
From: WANG, SHOU-TE
To: WINBOND ELECTRONICS CORP.
Reel/Frame 065233/0081 →
Priority Claims (1)
TW 111138019 · Oct 6, 2022 · national
Continuity (1)
Related Publication 20240121936A1 · Apr 11, 2024
References Cited (49)
US 5506166A · Sandhu · 1996 [cited by examiner]
US 7002199B2 · Fukuzumi · 2006 [cited by examiner]
US 9613967B1 · Chien · 2017 [cited by examiner]
US 10714483B2 · Chen · 2020 [cited by examiner]
US 10734390B1 · Park · 2020 [cited by examiner]
US 10910380B2 · Takesako · 2021 [cited by examiner]
US 10923479B2 · Chen · 2021 [cited by examiner]
US 10998230B2 · Basker et al. · 2021 [cited by applicant]
US 12581644B2 · Wang · 2026 [cited by examiner]
US 20030214872A1 · Tu · 2003 [cited by examiner]
US 20060138510A1 · Fazan · 2006 [cited by examiner]
US 20080064206A1 · Seo · 2008 [cited by examiner]
US 20100181623A1 · Im · 2010 [cited by examiner]
US 20110183512A1 · Cho · 2011 [cited by examiner]
US 20120276711A1 · Yoon · 2012 [cited by examiner]
US 20130154101A1 · Park · 2013 [cited by examiner]
US 20150255465A1 · Yokomichi · 2015 [cited by examiner]
US 20180108608A1 · Lee · 2018 [cited by examiner]
US 20180342517A1 · Takesako · 2018 [cited by examiner]
US 20190019795A1 · Takesako · 2019 [cited by examiner]
US 20190189620A1 · Wang · 2019 [cited by examiner]
US 20190312037A1 · Chang · 2019 [cited by examiner]
US 20190319029A1 · Chen · 2019 [cited by examiner]
US 20200203354A1 · Lee · 2020 [cited by examiner]
US 20200312707A1 · Chen · 2020 [cited by examiner]
US 20200388618A1 · Ikeda · 2020 [cited by examiner]
US 20210225763A1 · Tseng · 2021 [cited by examiner]
US 20210398982A1 · Li · 2021 [cited by examiner]
US 20210398983A1 · Lee · 2021 [cited by examiner]
US 20220037251A1 · Park · 2022 [cited by examiner]
US 20220052055A1 · Chun · 2022 [cited by examiner]
US 20220068928A1 · Lu · 2022 [cited by examiner]
US 20220139921A1 · Kim · 2022 [cited by examiner]
US 20220216210A1 · Wei · 2022 [cited by examiner]
US 20220254786A1 · Lu · 2022 [cited by examiner]
US 20220285361A1 · Yu · 2022 [cited by examiner]
US 20220320110A1 · Lu · 2022 [cited by examiner]
US 20220336465A1 · Kim · 2022 [cited by examiner]
US 20230055073A1 · Yang · 2023 [cited by examiner]
US 20230063527A1 · Lee · 2023 [cited by examiner]
US 20230209806A1 · Wu · 2023 [cited by examiner]
US 20230225115A1 · Wu · 2023 [cited by examiner]
US 20230232612A1 · Shin · 2023 [cited by examiner]
US 20230253317A1 · Tung · 2023 [cited by examiner]
US 20230328952A1 · Guo · 2023 [cited by examiner]
US 20240023307A1 · Chu · 2024 [cited by examiner]
US 20240172427A1 · Kwon · 2024 [cited by examiner]
US 20250365939A1 · Lee · 2025 [cited by examiner]
TW I735860B · 2021 [cited by applicant]