Semiconductor structure and method of manufacturing the same

1. A semiconductor structure, comprising:

a substrate with a cell region define thereon, and said substrate is provided with multiple recesses and active areas;

multiple bit lines spaced apart in a first direction on said cell region and extending in a second direction perpendicular to said first direction; and

a dummy bit line at an outermost side of said multiple bit lines in said first direction and extending in said second direction, wherein a width of said dummy bit line in said first direction is larger than a width of said bit lines in said first direction, and said bit lines and said dummy bit line have the same composition and layer structures, comprising a contact layer, a conductive layer and a hard mask layer sequentially from said substrate, wherein said contact layer of a bit line of said bit lines is in a recess of said recesses and electrically connected to an active area of said active areas through said recess and forms a first trench collectively with a sidewall of said recess, and a part of said contact layer of said dummy bit line is in another recess of said recesses and electrically connected to another active area of said active areas and forms a second trench collectively with a sidewall of said recess.

2. The semiconductor structure of claim 1 , wherein a depth of said first trench is the same as a depth of said recess, and a depth of said second trench is deeper than the depth of said first trench.

3. The semiconductor structure of claim 2 , wherein a conformal spacer layer is formed on sidewalls at two sides of said bit lines, on a sidewall at an inner side of said dummy bit line, on surfaces of said first trench and said second trench, and further comprising spacers formed on the sidewalls at the two sides of said bit lines and at two sides of said dummy bit line.

4. The semiconductor structure of claim 3 , wherein a spacer of said spacers is at the sidewall at the inner side of said dummy bit line, passes through said spacer layer and directly contacts one underlying active area of said active areas of said substrate.

5. The semiconductor structure of claim 2 , said first trench is filled with a first bit line spacer, said second trench is filled with a second bit line spacer, and further comprising spacers formed on sidewalls at two sides of said bit lines, on sidewalls at two sides of said dummy bit line, on said first bit line spacer and on said second bit line spacer.

6. The semiconductor structure of claim 5 , wherein a top surface of said second bit line spacer is lower than a top surface of said first bit line spacer.

7. The semiconductor structure of claim 5 , wherein said second bit line spacer is conformally formed on a surface of said second trench, and a part of a spacer of said spacers extends into said second bit line spacer.

8. The semiconductor structure of claim 5 , wherein a width of a spacer of said spacers in said first direction at an outer side of said dummy bit line is larger than a width of a spacer of said spacers in said first direction at an inner side of said dummy bit line and larger than a width of a spacer of said spacers in said first direction on said bit line.

9. The semiconductor structure of claim 5 , wherein bottoms of said spacers at the two sides of said dummy bit line are not on the same level.

10. The semiconductor structure of claim 5 , wherein a spacer of said spacers at an outer side of said dummy bit line is a single-layered spacer, and a spacer of said spacers at an inner side of said dummy bit line is a multilayered spacer.