Memory device and manufacturing method thereof

1. A manufacturing method of a memory device, comprising:

providing a substrate, wherein the substrate has a plurality of first regions and a plurality of second regions;

forming a plurality of word line sets in the first regions;

forming a first dielectric layer on the substrate of the first regions;

forming a conductive layer on the substrate of the second regions, wherein a top surface of the conductive layer is lower than a top surface of the first dielectric layer;

forming a sacrificial layer to surround the conductive layer;

conformally forming a second dielectric layer on the substrate;

performing an etching process to form openings in the conductive layer and the second dielectric layer of the second regions, wherein the openings expose a first isolation structure in the substrate of the second regions;

forming a second isolation structure in the openings;

performing a planarization process to expose the sacrificial layer;

recessing a portion of the conductive layer to form a first conductive structure and expose the sacrificial layer;

removing the sacrificial layer to form an air gap surrounding an upper portion of the first conductive structure; and

forming a second conductive structure on the first conductive structure to encapsulate the air gap.

2. The manufacturing method of the memory device of claim 1 , wherein the forming the sacrificial layer to surround the conductive layer comprises:

forming a first conductive material on the substrate of the second regions;

forming a sacrificial material to conformally cover the first conductive material and the first dielectric layer;

removing a portion of the sacrificial material to form the sacrificial layer and expose a top surface of the first conductive material and the top surface of the first dielectric layer; and

forming a second conductive material on the first conductive material, such that the sacrificial layer surrounds sidewalls of the second conductive material.

3. The manufacturing method of the memory device of claim 1 , wherein after the second dielectric layer is formed, the second dielectric layer has an uneven top surface, and a top surface of the second dielectric layer of the second regions is lower than a top surface of the second dielectric layer of the first regions.

4. The manufacturing method of the memory device of claim 1 , wherein a portion of the second dielectric layer of the first regions is further removed to expose the top surface of the first dielectric layer during the etching process.

5. The manufacturing method of the memory device of claim 1 , wherein the second isolation structure is in contact with the first isolation structure and separates the conductive layer and the sacrificial layer on the second regions.

6. A manufacturing method of a memory device, comprising:

providing a substrate, wherein the substrate has a plurality of active areas;

forming a first dielectric layer on the substrate;

forming a plurality of contact openings in the first dielectric layer, wherein the contact openings are respectively disposed on ends of the active areas;

respectively forming a plurality of conductive layers in the contact openings;

forming a sacrificial layer to surround the conductive layers;

recessing a portion of the conductive layers to form first conductive structures, wherein the first conductive structures include lower portions and upper portions on the lower portions, and a bottom width of the lower portions is greater than a bottom width of the upper portions;

removing the sacrificial layer to form air gaps surrounding the upper portions of the first conductive structures; and

forming second conductive structures on the first conductive structures to encapsulate the air gaps,

wherein the air gaps are in direct contact with the upper portions of the first conductive structures after the forming the second conductive structures on the first conductive structures.

7. The manufacturing method of the memory device of claim 6 , wherein the forming the sacrificial layer to surround the conductive layers comprises:

forming a first conductive material in the contact openings;

forming a sacrificial material to conformally cover the first conductive material and the first dielectric layer;

removing a portion of the sacrificial material to form the sacrificial layer and expose a top surface of the first conductive material and a top surface of the first dielectric layer; and

forming a second conductive material on the first conductive material, such that the sacrificial layer surrounds sidewalls of the second conductive material.

8. The manufacturing method of the memory device of claim 7 , wherein after the sacrificial layer is completely removed, the air gaps completely surround the upper portions of the first conductive structures.