IP Library › Granted Patent US 12,082,392
Granted Patent B2
US 12,082,392 · App. 17/444,670 · Granted Sep 3, 2024

Semiconductor structure and method for preparing seminconductor structure

Inventors: Jingwen Lu (Hefei, CN); Bingyu Zhu (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10B12/03H01L23/528
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Quick Facts
Patent No.
US 12,082,392
App. No.
17/444,670
Granted
Sep 3, 2024
Kind
B2
Abstract

A semiconductor structure includes a conductive structure. A method for preparing the conductive structure includes: forming a semiconductor conductive layer; forming a nitrile or isonitrile transition layer on the semiconductor conductive layer; and forming a metal conductive layer on the nitrile or isonitrile transition layer.

Claims (33)

1. A method for preparing a semiconductor structure, the semiconductor structure comprising a conductive structure, the method for preparing the conductive structure comprising the following operations:

forming a semiconductor conductive layer;

forming a nitrile or isonitrile transition layer on the semiconductor conductive layer; and

forming a metal conductive layer on the nitrile or isonitrile transition layer.

2. The method for preparing the semiconductor structure according to claim 1 , wherein the method, after forming the metal conductive layer on the nitrile or isonitrile transition layer, further comprises:

forming a passivation layer on the metal conductive layer.

3. The method for preparing the semiconductor structure according to claim 2 , wherein the semiconductor conductive layer is formed on a semiconductor substrate, and the method, after forming the passivation layer on the metal conductive layer, further comprises:

patterning the passivation layer, the metal conductive layer, the nitrile or isonitrile transition layer and the semiconductor conductive layer to form a plurality of bit line structures discretely arranged on the semiconductor substrate.

4. The method for preparing the semiconductor structure according to claim 3 , wherein the method further comprises:

forming a protective layer on a sidewall of each bit line structure.

5. The method for preparing the semiconductor structure according to claim 1 , wherein forming the semiconductor conductive layer comprises:

providing a semiconductor base provided with a plurality of capacitor contact holes; and

forming the semiconductor conductive layer in each capacitor contact hole.

6. The method for preparing the semiconductor structure according to claim 1 , wherein forming the nitrile or isonitrile transition layer on the semiconductor conductive layer comprises:

treating a surface of the semiconductor conductive layer with a nitrile or isonitrile organic solution to form the nitrile or isonitrile transition layer.

7. The method for preparing the semiconductor structure according to claim 2 , wherein forming the nitrile or isonitrile transition layer on the semiconductor conductive layer comprises:

treating a surface of the semiconductor conductive layer with a nitrile or isonitrile organic solution to form the nitrile or isonitrile transition layer.

8. The method for preparing the semiconductor structure according to claim 3 , wherein forming the nitrile or isonitrile transition layer on the semiconductor conductive layer comprises:

treating a surface of the semiconductor conductive layer with a nitrile or isonitrile organic solution to form the nitrile or isonitrile transition layer.

9. The method for preparing the semiconductor structure according to claim 4 , wherein forming the nitrile or isonitrile transition layer on the semiconductor conductive layer comprises:

treating a surface of the semiconductor conductive layer with a nitrile or isonitrile organic solution to form the nitrile or isonitrile transition layer.

10. The method for preparing the semiconductor structure according to claim 5 , wherein forming the nitrile or isonitrile transition layer on the semiconductor conductive layer comprises:

treating a surface of the semiconductor conductive layer with a nitrile or isonitrile organic solution to form the nitrile or isonitrile transition layer.

11. The method for preparing the semiconductor structure according to claim 6 , wherein a concentration of nitrile or isonitrile in the nitrile or isonitrile organic solution is 5%-10%.

12. The method for preparing the semiconductor structure according to claim 6 , wherein the method, after forming the nitrile or isonitrile transition layer on the semiconductor conductive layer, further comprises a rinsing operation.

13. The method for preparing the semiconductor structure according to claim 1 , wherein the semiconductor conductive layer is a polysilicon layer, and the metal conductive layer comprises a Ti and TiN composite layer and a metal tungsten layer which are sequentially formed.

14. The method for preparing the semiconductor structure according to claim 2 , wherein the semiconductor conductive layer is a polysilicon layer, and the metal conductive layer comprises a Ti and TiN composite layer and a metal tungsten layer which are sequentially formed.

15. The method for preparing the semiconductor structure according to claim 13 , wherein the method, after forming the Ti and TiN composite layer and before forming the metal tungsten layer, further comprises a rapid thermal processing operation.

16. A semiconductor structure prepared with the method of claim 1 , comprising the conductive structure comprising the semiconductor conductive layer, the nitrile or isonitrile transition layer and the metal conductive layer which are sequentially stacked on one another.

17. The semiconductor structure according to claim 16 , wherein the semiconductor structure further comprises a semiconductor base, the semiconductor base comprises a semiconductor substrate and a plurality of bit line structures discretely arranged on the semiconductor substrate, a plurality of isolation structures are arranged along a direction perpendicular to the bit line structures, and the isolation structures and the bit line structures form a plurality of capacitor contact holes.

18. The semiconductor structure according to claim 17 , wherein each bit line structure comprises the conductive structure and a passivation layer covering the conductive structure.

19. The semiconductor structure according to claim 17 , wherein a protective layer is formed on a sidewall of each bit line structure.

20. The semiconductor structure according to claim 17 , wherein the conductive structure is provided in each of the capacitor contact holes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2021
From: LU, JINGWEN; ZHU, BINGYU
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 057115/0519 →
Priority Claims (1)
CN 202010876670.5 · Aug 27, 2020 · national
Continuity (2)
Continuation PCTCN2021099889 · Jun 12, 2021
Related Publication 20220068928A1 · Mar 3, 2022