Systems and methods for performing 16-bit floating-point matrix dot product instructions
Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
1. A processor comprising:
fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a M by N destination matrix having single-precision elements, a M by K first source matrix, and a K by N second source matrix, the specified source matrices having elements comprising a pair of 16-bit floating-point values, the opcode to indicate execution circuitry is to, for each element (m, n) of the specified destination matrix, convert K pairs of values from row m of the specified first source matrix and K pairs of values from column n of the specified second source matrix to single-precision, multiply converted first values of the pairs from the two specified source matrices to generate first products and multiply converted second values of the pairs from the two specified source matrices to generate second products, and then accumulate a sum of the first products and a sum of the second products with previous content of the element of the specified destination matrix;
decode circuitry to decode the fetched instruction; and
the execution circuitry to respond to the decoded instruction as specified by the opcode.
2. The processor of claim 1 , wherein the 16-bit floating-point format is either bfloat16 or binary16, the format to be specified by the instruction.
3. The processor of claim 1 , wherein M, N, and K are either specified by the instruction or are to be programmed using a matrix configuration instruction before fetching the instruction.
4. The processor of claim 1 , wherein the execution circuitry is further to saturate execution results, as necessary.
5. The processor of claim 1 , wherein the instruction is further to specify a writemask comprising M×N bits, each bit to control whether to mask a corresponding element of the specified destination matrix, wherein masked elements of the destination matrix are to either be zeroed or merged.
6. The processor of claim 1 , wherein the specified source and destination matrix locations are each in one of a collection of registers or a plurality of memory locations to represent a matrix.
7. The processor of claim 1 , wherein the execution circuitry is further to generate a fault when a fault condition occurs, the fault condition comprising one or more of:
one or more of the first and second specified source matrices having a valid parameter not set to true;
the specified destination matrix having a different number of rows than a number of rows of the specified first source matrix;
the specified destination matrix having a different number of columns than a number of columns of the specified first source matrix; and
one or more of the specified first source, second source, and destination matrices having dimensions that exceed maximum dimensions, the dimensions comprising numbers of matrix rows and columns.
8. A method comprising:
fetching, using fetch circuitry, an instruction having fields to specify an opcode and locations of a M by N destination matrix having single-precision elements, a M by K first source matrix, and a K by N second source matrix, the specified source matrices having elements comprising a pair of 16-bit floating-point values, the opcode to indicate execution circuitry is to, for each element (m, n) of the specified destination matrix, convert K pairs of values from row m of the specified first source matrix and K pairs of values from column n of the specified second source matrix to single-precision, multiply converted first values of the pairs from the two specified source matrices to generate first products and multiply converted odd second values of the pairs from the two specified source matrices to generate second products, and then accumulate a sum of the first products and a sum of the second products with previous content of the element of the specified destination matrix;
decoding, using decode circuitry, the fetched instruction; and
responding, with the execution circuitry, to the decoded instruction as specified by the opcode.
9. The method of claim 8 , wherein the 16-bit floating-point format is either bfloat16 or binary16, the format to be specified by the instruction.
10. The method of claim 8 , wherein M, N, and K are either specified by the instruction or are to be programmed using a matrix configuration instruction before fetching the instruction.
11. The method of claim 8 , wherein the execution circuitry is further to saturate execution results, as necessary.
12. The method of claim 8 , wherein the instruction is further to specify a writemask comprising M×N bits, each bit to control whether to mask a corresponding element of the specified destination matrix, wherein masked elements of the destination matrix are to either be zeroed or merged.
13. The method of claim 8 , wherein the specified source and destination matrix locations are each in one of a collection of registers ora plurality of memory locations to represent a matrix.
14. The method of claim 8 , wherein the execution circuitry is further to generate a fault when a fault condition occurs, the fault condition comprising one or more of:
one or more of the first and second specified source matrices having a valid parameter not set to true;
the specified destination matrix having a different number of rows than a number of rows of the specified first source matrix;
the specified destination matrix having a different number of columns than a number of columns of the specified first source matrix; and
one or more of the specified first source, second source, and destination matrices having dimensions that exceed maximum dimensions, the dimensions comprising numbers of matrix rows and columns.
15. A system comprising a memory and a processor, the processor comprising:
fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a M by N destination matrix having single-precision elements, a M by K first source matrix, and a K by N second source matrix, the specified source matrices having elements comprising a pair of 16-bit floating-point values, the opcode to indicate execution circuitry is to, for each element (m, n) of the specified destination matrix, convert K pairs of values from row m of the specified first source matrix and K pairs of values from column n of the specified second source matrix to single-precision, multiply converted first values of the pairs from the two specified source matrices to generate first products and multiply converted odd second values of the pairs from the two specified source matrices to generate second products, and then accumulate a sum of the first products and a sum of the second products with previous content of the element of the specified destination matrix;
decode circuitry to decode the fetched instruction; and
the execution circuitry to respond to the decoded instruction as specified by the opcode.
16. The system of claim 15 , wherein the 16-bit floating-point format is either bfloat16 or binary16, the format to be specified by the instruction.
17. The system of claim 15 , wherein M, N, and K are either specified by the instruction or are to be programmed using a matrix configuration instruction before fetching the instruction.
18. The system of claim 15 , wherein the execution circuitry is further to saturate execution results, as necessary.
19. The system of claim 15 , wherein the instruction is further to specify a writemask comprising M×N bits, each bit to control whether to mask a corresponding element of the specified destination matrix, wherein masked elements of the destination matrix are to either be zeroed or merged.
20. The system of claim 15 , wherein the specified source and destination matrix locations are each in one of a collection of registers or a plurality of memory locations to represent a matrix.