IP Library Granted Patent US 11,432,402
Granted Patent B2
US 11,432,402 · App. 16/186,872 · Granted Aug 30, 2022

Flipped-conductor-patch lamination for ultra fine-line substrate creation

Inventors: John Adam Tracy deMercleden Smithells (Caldicot, GB); Nina Biddle (Coleford, GB)
Assignee: Microchip Technology Caldicot Limited
H05K1/112H05K1/0298H05K1/144H05K1/0366H05K1/0393H05K1/111H05K1/119H05K1/181
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Quick Facts
Patent No.
US 11,432,402
App. No.
16/186,872
Granted
Aug 30, 2022
Kind
B2
Abstract

A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm 2 . The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces.

Claims (37)

1. A laminated circuit board structure comprising:

a printed circuit board substrate including wiring traces on a first wiring face of the printed circuit board substrate;

a prepreg layer formed over the first wiring face of the printed circuit board substrate, the prepreg layer having no wiring traces;

a plurality of patches, respective ones of the patches comprising:

a flexible non-conductive substrate having a wiring face; and

wiring traces formed on the wiring face of the flexible non-conductive substrate, the flexible non-conductive substrate having an area smaller than an area of the prepreg layer, the lateral extent of the wiring traces not extending laterally beyond the lateral extent of the flexible non-conductive substrate,

respective ones of the patches laminated to the prepreg layer with the wiring face of the flexible non-conductive substrate facing the first wiring face of the printed circuit board structure and the wiring face of the flexible non-conductive substrate in contact with and pressed into the prepreg layer, wherein portions of the prepreg layer fill interstices between the wiring traces on the wiring face of the flexible non-conductive substrate and wherein the flexible non-conductive substrate provides a solder resist layer for the laminated circuit board structure.

2. The laminated circuit board structure of claim 1 comprising;

at least one opening formed through the flexible non-conductive substrate of respective ones of the patches and communicating with at least one wiring trace on the wiring face of the flexible non-conductive substrate; and

a conductive material disposed in each of the at least one opening and in electrical contact with the at least one wiring trace on the wiring face of the flexible non-conductive substrate.

3. The laminated circuit board structure of claim 2 wherein the conductive material disposed in each of the at least one opening and in electrical contact with the at least one wiring traces formed on the wiring face of the flexible non-conductive substrate is a solder bump.

4. The laminated circuit board structure of claim 2 wherein the conductive material disposed in each of the at least one opening and in electrical contact with the at least one wiring traces formed on the wiring face of the flexible non-conductive substrate is a layer of conductive ink.

5. The laminated circuit board structure of claim 1 comprising:

conductive traces on a second wiring face of the printed circuit board substrate;

a first conductive via formed through the printed circuit board substrate making electrical contact between one of the wiring traces on the first wiring face of the printed circuit board substrate and one of the conductive traces on the second wiring face of the printed circuit board substrate; and

a second conductive via formed through the prepreg layer and in electrical contact with one of the wiring traces formed on the wiring face of the flexible non-conductive substrate.

6. The laminated circuit board structure of claim 5 wherein the second conductive via is further in electrical contact with one of the wiring traces on the first wiring face of the printed circuit board substrate.

7. The laminated circuit board structure of claim 1 where the non-conductive substrate is formed from polyimide.

8. A laminated circuit board structure comprising:

a printed circuit board substrate including wiring traces on a first wiring face of the printed circuit board substrate;

a prepreg layer formed over the first wiring face of the printed circuit board substrate, the prepreg layer having no wiring traces;

a plurality of patches, respective ones of the patches comprising:

a flexible non-conductive substrate having a wiring face;

wiring traces formed on the wiring face of the flexible non-conductive substrate, the flexible non-conductive substrate having an area smaller than an area of the prepreg layer and less than 1000 mm 2 , the lateral extent of the wiring traces formed on the wiring face of the flexible non-conductive substrate not extending laterally beyond the lateral extent of the flexible non-conductive substrate,

the respective ones of the patches laminated to the prepreg layer with the wiring face of the flexible non-conductive substrate facing the first wiring face of the printed circuit board structure and the wiring face of the flexible non-conductive substrate in contact with and pressed into the prepreg layer, wherein portions of the prepreg layer fill interstices between the wiring traces formed on the wiring face of the flexible non-conductive substrate and wherein the flexible non-conductive substrate provides a solder resist layer for the laminated circuit board structure;

a conductive material disposed in at least one opening that extends through the flexible non-conductive substrate of one of the patches, the conductive material in electrical contact with the at least one wiring trace formed on the wiring face of the flexible non-conductive substrate of the one of the patches; and

an integrated circuit die or surface mount component in electrical contact with the conductive material disposed in the at least one opening that extends through the flexible non-conductive substrate of one of the patches.

9. A laminated circuit board structure comprising:

a printed circuit board substrate including wiring traces on a first wiring face of the printed circuit board substrate;

a prepreg layer formed over the first wiring face of the printed circuit board substrate, the prepreg layer having no wiring traces;

a plurality of patches, respective ones of the patches comprising;

a flexible non-conductive substrate having a wiring face, the flexible non-conductive substrate formed of polyester or polyimide;

a die attach area, wiring traces and input and output pads formed in a copper layer disposed on the wiring face of the flexible non-conductive substrate, the flexible non-conductive substrate having a uniform thickness and an area smaller than an area of the prepreg layer, the lateral extent of the wiring traces not extending laterally beyond the lateral extent of the flexible non-conductive substrate,

respective ones of the patches laminated to the prepreg layer with the wiring face of the flexible non-conductive substrate facing the first wiring face of the printed circuit board structure and the wiring face of the flexible non-conductive substrate in contact with and pressed into the prepreg layer, wherein portions of the prepreg layer fill interstices between the wiring traces on the wiring face of the flexible non-conductive substrate and wherein the flexible non-conductive substrate provides a solder resist layer for the laminated circuit board structure;

a conductive material disposed in at least one opening that extends through the flexible non-conductive substrate of one of the patches, the conductive material in electrical contact with the at least one wiring trace formed on the wiring face of the flexible non-conductive substrate of the one of the patches; and

an integrated circuit die in electrical contact with the conductive material disposed in at least one opening that extends through the flexible non-conductive substrate of the one of the patches.

10. The patch of claim 9 wherein the area of the flexible non-conductive substrate is smaller than 1000 mm 2 .

Assignments (3)
CHANGE OF NAME Recorded Mar 23, 2021
From: MICROSEMI SEMICONDUCTOR LIMITED
To: MICROCHIP TECHNOLOGY CALDICOT LIMITED
Reel/Frame 055691/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2019
From: BIDDLE, NINA
To: MICROSEMI SEMICONDUCTOR LIMITED
Reel/Frame 049676/0595 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2018
From: SMITHELLS, JOHN ADAM TRACY DEMERCLEDEN
To: MICROSEMI SEMICONDUCTOR LIMITED
Reel/Frame 047475/0224 →
Continuity (3)
Provisional Application 62744515 · Oct 11, 2018
Related Publication 20200120797A1 · Apr 16, 2020
Related Publication 20210092842A9 · Mar 25, 2021