Technique for managing power domains in an integrated circuit
An integrated circuit and method are provided for managing power domains. The integrated circuit has first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state. Further, the additional power control circuitry is arranged to output a mode status signal that is then used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain. This ensures that, despite the power control circuitry losing knowledge of the current power state of the first power domain whilst it is in the power saving state, no unintended consequences occur when the second power domain subsequently exits the power saving state.
1. An integrated circuit comprising:
first circuitry provided within a first power domain; and
a distributed power controller to control transition of the first power domain between a plurality of power states, the distributed power controller comprising at least power control circuitry in a second power domain and additional power control circuitry in a third power domain;
wherein:
whilst a current power state of the first power domain is any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain, and the third power domain is prevented from entering that power saving state; and
the additional power control circuitry is arranged to output a mode status signal used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain.
2. An integrated circuit as claimed in claim 1 , wherein:
the first circuitry includes a storage structure arranged to store data;
the plurality of power states of the first power domain includes a retention power state where a power supply is retained to the storage structure to cause retention of data stored in the storage structure, whilst other components within the first circuitry are powered off;
the second power domain is allowed to be placed in the power saving state whilst the first power domain is in the retention power state; and
the mode status signal output by the additional power control circuitry identifies a retention mode when the current power state of the first power domain is the retention power state.
3. An integrated circuit as claimed in claim 2 , wherein:
said at least two of the power states comprise at least the retention power state and an off power state, in the off power state the storage structure being powered off in addition to the components of the first circuitry powered off during the retention power state; and
the mode status signal output by the additional power control circuitry causes the power control circuitry to be configured such that the initial mode of operation differs depending on whether the current power state of the first power domain is the off power state or the retention power state.
4. An integrated circuit as claimed in claim 2 , wherein the storage structure is a memory, and the retention power state is a memory retention power state.
5. An integrated circuit as claimed in claim 1 , wherein:
the power control circuitry is powered off when the second power domain is in the power saving state;
the power control circuitry has a default mode of operation to which the power control circuitry is to transition when power is restored to the power control circuitry; and
the mode status signal output by the additional power control circuitry causes the power control circuitry to initially enter the initial mode of operation instead of the default mode of operation.
6. An integrated circuit as claimed in claim 5 , wherein:
the first circuitry includes a storage structure arranged to store data;
the plurality of power states of the first power domain includes a retention power state where a power supply is retained to the storage structure to cause retention of data stored in the storage structure, whilst other components within the first circuitry are powered off;
the second power domain is allowed to be placed in the power saving state whilst the first power domain is in the retention power state; and
the mode status signal output by the additional power control circuitry identifies a retention mode when the current power state of the first power domain is the retention power state;
the default mode of operation is a power on mode of operation, and the provision of the mode status signal from the additional power control circuitry prevents the power control circuitry transitioning directly from a power off mode to the power on mode of operation at least when the current power state of the first power domain is the retention power state.
7. An integrated circuit as claimed in claim 1 , wherein when the second power domain exits the power saving state, the power control circuitry is triggered by a reset event to sample the mode status signal from the additional power control circuitry.
8. An integrated circuit as claimed in claim 7 , wherein the reset event occurs when the power control circuitry is released from reset following the second power domain exiting the power saving state.
9. An integrated circuit as claimed in claim 1 , wherein the current power state of the first power domain is the power state that the first power domain was in when the second power domain entered the power saving state.
10. An integrated circuit as claimed in claim 1 , wherein when the second power domain is in the power saving state the power control circuitry loses knowledge of its mode of operation that was in place prior to the power saving state being entered.
11. An integrated circuit as claimed in claim 1 , wherein the third power domain is retained in a powered state whilst the first power domain is in any one of the at least two of the plurality of power states, the powered state ensuring that the additional power control circuitry retains information about the current power state of the first power domain.
12. An integrated circuit as claimed in claim 11 , wherein the third power domain is constrained to remain in the powered state whilst the power supply is retained to any components within the first power domain and the second power domain.
13. An integrated circuit as claimed in claim 1 , wherein the third power domain is an always on power domain such that a power supply is retained to the third power domain whilst the integrated circuit is turned on.
14. An integrated circuit as claimed in claim 1 , wherein the power control circuitry is arranged to control one or more operations performed by components of the first circuitry in association with transitioning of the power state of the first power domain.
15. An integrated circuit as claimed in claim 14 , wherein the additional power control circuitry is arranged to control power switching circuitry used to modify the power supply provided to one or more components of the first circuitry when transitioning the power state of the first power domain.
16. An integrated circuit as claimed in claim 1 , wherein the distributed power controller further comprises further power control circuitry to control transition of the second power domain between multiple power states, the further power control circuitry being in a power domain other than the first power domain and the second power domain.
17. An integrated circuit as claimed in claim 16 , wherein the further power control circuitry at least partly resides within the third power domain.
18. A method of managing power domains in an integrated circuit having first circuitry provided within a first power domain, and a distributed power controller to control transition of the first power domain between a plurality of power states, the distributed power controller comprising at least power control circuitry in a second power domain and additional power control circuitry in a third power domain, the method comprising:
placing the second power domain into a power saving state whilst a current power state of the first power domain is any one of at least two of the plurality of power states, in the power saving state the power control circuitry losing knowledge of the current power state of the first power domain;
retaining the third power domain in a power state during which the additional power control circuitry outputs a mode status signal indicative of the current power state of the first power domain; and
when the second power domain exits the power saving state, using the mode status signal to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain.
19. An integrated circuit comprising:
first circuit means provided within a first power domain;
distributed power controller means for controlling transition of the first power domain between a plurality of power states, the distributed power controller means comprising at least power control means in a second power domain and additional power control means in a third power domain;
wherein:
whilst a current power state of the first power domain is any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control means loses knowledge of the current power state of the first power domain, and the third power domain is prevented from entering that power saving state; and
the additional power control means for outputting a mode status signal used by the power control means, when the second power domain exits the power saving state, for placing the power control means into an initial mode of operation that is dependent on the current power state of the first power domain.