System on chip, bus power gating method thereof, and bus power gating system
A power gating method of a system on chip includes transferring a first control signal to a bus by using a power management unit (PMU), transferring a response signal to the PMU by using the bus, in response to the first control signal, moving a transaction to a light bus circuit by using the bus, and transferring a second control signal to a power control circuit by using the PMU to adjust power supplied to the bus, based on the response signal.
1 . A power gating method of a system on chip including a power management unit (PMU) including at least one register, a power control circuit, and a bus including a main bus circuit, a light bus circuit, and a bus controller including processing circuitry configured to process a pending transaction that has not yet been processed and is pending at the bus, the power gating method comprising:
transferring a first control signal from the PMU to the bus;
transferring, in response to the first control signal, a response signal to the PMU prior to completion of the pending transaction;
moving, by the bus controller, the pending transaction pending i) either at a combination of the main bus circuit and the light bus circuit or ii) exclusively at the main bus circuit to the light bus circuit after transferring the response signal from the bus to the PMU such that the pending transaction is moved internally within the bus to the light bus circuit subsequent to the pending transaction being received by the bus; and
transferring a second control signal to the power control circuit by using the PMU to adjust power supplied to the bus, based on the response signal.
2 . The power gating method of claim 1 , wherein a transaction threshold value of the main bus circuit is greater than a transaction threshold value of the light bus circuit, and
the power supplied to the bus is adjusted in response the bus being in an idle state.
3 . The power gating method of claim 1 , wherein the pending transaction is one of a plurality of pending transactions, and the transferring the first control signal to the bus comprises generating the first control signal by using the PMU based on an amount of the plurality of pending transactions being processed by the bus and a transaction threshold value of the light bus circuit.
4 . The power gating method of claim 3 , wherein the transferring the first control signal to the bus comprises, in response to the amount of the plurality of pending transactions being processed by the bus being less than the transaction threshold value, providing the first control signal to the bus by using the PMU.
5 . The power gating method of claim 1 , wherein the power supplied to the bus is adjusted by selectively providing first power or second power to the light bus circuit by using the power control circuit in response to the second control signal.
6 . The power gating method of claim 5 , wherein the selectively providing the first power or the second power to the light bus circuit comprises cutting off power supplied to the main bus circuit by using the power control circuit in response to the second control signal.
7 . The power gating method of claim 5 , wherein the pending transaction is one of a plurality of pending transactions, and the power supplied to the bus is adjusted by,
identifying the pending transaction moved to the light bus circuit by using the bus, and
cutting off the first power or the second power provided to the bus by using the power control circuit based on an amount of the plurality of pending transactions.
8 . The power gating method of claim 7 , wherein the cutting off the first power or the second power comprises, in response the amount of the plurality of pending transactions being zero, cutting off the first power or the second power provided to the light bus circuit by using the power control circuit.
9 . A system on chip comprising:
a bus including a main bus circuit, a light bus circuit and a bus controller including processing circuitry, the bus being configured to process a pending transaction that has not yet been processed and is at the bus by using one or more of the main bus circuit and the light bus circuit and allow the pending transaction to be processed by the light bus circuit based on a transaction threshold value of the light bus circuit, the pending transaction being one of a plurality of transactions that has not yet been processed and is at the bus;
a power control circuit including a main bus power switch, a light bus power switch, and a power path controller, the power control circuit being configured to control power supplied to the bus; and
a power management unit (PMU) including at least one register, the PMU configured to,
generate a first control signal and a second control signal based on an amount of the plurality of transactions,
transfer the first control signal to the bus to control an operation of the bus, wherein, in response to the first control signal, the bus is configured to transfer a response signal to the PMU prior to the bus controller moving the pending transaction that is pending i) either at a combination of the main bus circuit and the light bus circuit or ii) exclusively at the main bus circuit to the light bus circuit after transferring the response signal to the PMU such that the pending transaction is moved internally within the bus to the light bus circuit subsequent to the pending transaction being received by the bus, and
transfer the second control signal to the power control circuit to control an operation of the power control circuit.
10 . The system on chip of claim 9 , wherein the power path controller is configured to select at least one of a first power source providing a first power and a second power source providing second power and supply the first power or the second power to the light bus circuit based on the selection and in response to the second control signal.
11 . The system on chip of claim 9 , wherein the main bus power switch is configured to cut off first power supplied to the main bus circuit through the main bus power switch, in response to the second control signal.
12 . The system on chip of claim 9 , wherein the light bus power switch is configured to cut off first power or second power supplied to the light bus circuit through the power path controller in response to the second control signal.
13 . The system on chip of claim 9 , wherein the at least one register of the PMU is configured to store information about the transaction threshold value of the light bus circuit.
14 . The system on chip of claim 13 , wherein, the PMU is further configured to, in response to an amount of the plurality of transactions being less than the transaction threshold value, generate the first control signal and the second control signal.
15 . The system on chip of claim 9 , wherein, in response to the amount of the plurality of transactions being greater than or equal to the transaction threshold value,
the bus is configured to process the pending transaction by using the main bus circuit and the light bus circuit, and
the power control circuit is configured to supply main power to the bus.
16 . The system on chip of claim 9 , wherein, in response to the amount of the plurality of transactions being less than the transaction threshold value,
the bus is configured to process the pending transaction by using the light bus circuit, and
the power control circuit is configured to supply second power to the bus based on control by the PMU and control the main bus power switch to cut off supply of first power.
17 . The system on chip of claim 16 , wherein the power control circuit is configured to, after the light bus circuit processes all of the plurality of pending transactions, control the light bus power switch to cut off power supplied to the bus, based on control by the PMU.
18 . A bus comprising:
a main bus circuit, a light bus circuit and a bus controller including processing circuitry, the main bus circuit and the light bus circuit each configured to process a pending transaction, the pending transaction being one of the plurality of pending transactions of the bus that has not yet been processed, wherein,
in response to an amount of the plurality of pending transactions being greater than or equal to a transaction threshold value of the light bus circuit, the bus is configured to process the pending transaction by using the main bus circuit and the light bus circuit, and
in response to the amount of the plurality of pending transactions being less than the transaction threshold value, the bus is configured to process the pending transaction by using the light bus circuit by,
transferring, in response to a first control signal from a power management unit (PMU), a response signal to the PMU prior to completion of the pending transaction on the bus, the PMU including at least one register, and
moving, by the bus controller, the pending transaction that is pending i) either at a combination of the main bus circuit and the light bus circuit or ii) exclusively at the main bus circuit to the light bus circuit after transferring the response signal such that the pending transaction is moved internally within the bus to the light bus circuit subsequent to the pending transaction being received by the bus.
19 . The bus of claim 18 , wherein the bus is configured to be supplied with power from at least one of first power and second power,
in response to the amount of the plurality of pending transactions being greater than or equal to the transaction threshold value, the bus is configured to be supplied with power from the first power to process the pending transaction, and
in response to the amount of the plurality of pending transactions being less than the transaction threshold value, the bus is configured to be supplied with power from the second power to process the pending transaction.
20 . The bus of claim 18 , wherein the bus further comprises:
at least one bridge configured to connect the main bus circuit and the light bus circuit.