IP Library › Granted Patent US 12,430,140
Granted Patent B2
US 12,430,140 · App. 17/468,179 · Granted Sep 30, 2025

Per-lane power management of bus interconnects

Inventors: Travis T. Schluessler (Berthoud, CO); Huimin Chen (Beaverton, OR); Selvakumar Panneer (Portland, OR); Zhengmin Li (Portland, OR)
Assignee: Intel Corporation
G06F9/44505G06F9/4418G06F13/20
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Quick Facts
Patent No.
US 12,430,140
App. No.
17/468,179
Granted
Sep 30, 2025
Kind
B2
Abstract

A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

Claims (44)

1. A method, comprising:

receiving a request for a transfer of data on a communication bus of a computing device;

determining a direction for the transfer, at least in part based on the request;

determining a quantity of data for the transfer, at least in part based on the request;

determining a power state for a lane of the communication bus, the lane to be used for the transfer, the power state determination being at least in part based on the direction and the quantity of data for the transfer;

setting the power state for the lane of the communication bus; and

scheduling a wake or sleep initiation time for the lane of the communication bus.

2. The method of claim 1 , further comprising:

determining a period of time for the transfer, at least in part based on the request.

3. The method of claim 2 , wherein the power state for the lane of the communication bus at least in part is based on the period of time for the transfer.

4. The method of claim 1 , further comprising:

performing the transfer via the lane of the communication bus.

5. The method of claim 1 , further comprising: waking or sleeping the lane of the communication bus at the wake or sleep initiation time.

6. The method of claim 1 , further comprising:

determining whether the transfer is driven by a central processor unit of the computing device or by a peripheral device.

7. A non-transitory, computer-readable medium encoded with instructions that, when executed by a computer, cause the computer to perform a method comprising:

receiving a request for a transfer of data on a communication bus of the computer;

determining a direction for the transfer, at least in part based on the request;

determining a quantity of data for the transfer, at least in part based on the request;

determining separate power states for at least two different lanes of the communication bus, at least in part based on the direction and the quantity of data for the transfer; and

setting the power states for the lanes of the communication bus.

8. The medium of claim 7 , the method further comprising:

determining a period of time for the transfer, at least in part based on the request.

9. The medium of claim 8 , wherein the power state for the lane of the communication bus at least in part is based on the period of time for the transfer.

10. The medium of claim 7 , the method further comprising:

performing the transfer via the lane of the communication bus.

11. The medium of claim 7 , the method further comprising:

calculating a wake or sleep initiation time for the lane of the communication bus.

12. The medium of claim 11 , the method further comprising:

waking or sleeping the lane of the communication bus at the wake or sleep initiation time.

13. The medium of claim 7 , the method further comprising:

determining whether the transfer is driven by a central processor unit of the computer or by a peripheral device.

14. An apparatus, comprising:

a memory to include instructions; and

a processor configured to execute the instructions to receive a request for a transfer of data on a communication bus of a computer;

determine a direction for the transfer, at least in part based on the request;

determine a quantity of data for the transfer, at least in part based on the request;

determine separate power states for at least two different lanes of the communication bus, at least in part based on the direction and the quantity of data for the transfer; and

set the power states for the lanes of the communication bus.

15. The apparatus of claim 14 , wherein the processor further is configured to execute the instructions to determine a period of time for the transfer, at least in part based on the request.

16. The apparatus of claim 15 , wherein the power state for the lane of the communication bus at least in part is based on the period of time for the transfer.

17. The apparatus of claim 14 , wherein the processor further is configured to execute the instructions to perform the transfer via the lane of the communication bus.

18. The apparatus of claim 14 , wherein the processor further is configured to execute the instructions to calculate a wake or sleep initiation time for the lane of the communication bus.

19. The apparatus of claim 18 , wherein the processor further is configured to execute the instructions to wake or sleep the lane of the communication bus at the wake or sleep initiation time.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2021
From: SCHLUESSLER, TRAVIS T.; CHEN, HUIMIN; PANNEER, SELVAKUMAR; LI, ZHENGMIN
To: INTEL CORPORATION
Reel/Frame 057402/0392 →
Continuity (1)
Related Publication 20230076468A1 · Mar 9, 2023
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