Fabrication method of semiconductor device by removing sacrificial layer on gate structures
A semiconductor device and fabrication method thereof are provided. The method includes: providing a base substrate with first gate structures on the base substrate; forming a spacer covering sidewalls of each first gate structure; forming sacrificial layers on sides of each first gate structure to cover corresponding spacers; forming a bottom dielectric layer covering sidewalls of the sacrificial layers; after forming the bottom dielectric layer, removing the sacrificial layers by etching to form first openings between the bottom dielectric layer and the spacer; and forming a plug in each first opening.
1. A fabrication method for a semiconductor device, comprising:
forming a base substrate and first gate structures on the base substrate;
forming an offset spacer covering sidewalls of each first gate structure;
forming source/drain doped layers in the base substrate on sides of each first gate structure;
forming a spacer covering side surface of the offset spacer on the source/drain doped layers, wherein the source/drain doped layers have a side surface coplanar with an interface plane between the side surface of the offset spacer and side surface of the spacer;
forming sacrificial layers on sidewalls of each first gate structure to cover corresponding spacers;
forming a bottom dielectric layer covering sidewalls of the sacrificial layers;
after forming the bottom dielectric layer, removing the sacrificial layers to form first openings between the bottom dielectric layer and the spacers; and
forming a plug in each first opening.
2. The method according to claim 1 , wherein the spacer is made of a material including silicon oxide, silicon carbon nitride, or a combination thereof.
3. The method according to claim 1 , wherein the spacer has a dielectric constant of 2.5 to 3.7.
4. The method according to claim 1 , wherein the spacer has a thickness of 5 nm to 12 nm.
5. The method according to claim 1 , wherein the sacrificial layers are made of a material including amorphous silicon, polysilicon, or a combination thereof.
6. The method according to claim 1 , wherein:
each first gate structure has first sides opposite to each other and second sides opposite to each other;
the sacrificial layers cover a portion of the spacers on sidewalls of the first sides of the first gate structures; and
the sacrificial layers are formed by:
forming a sacrificial film over the base substrate to cover the base substrate, the spacers, and the first gate structures;
planarizing the sacrificial film to remove a first portion of the sacrificial film on a top surface of each first gate structure; and
removing a second portion of the sacrificial film on the second sides of each first gate structure.
7. The method according to claim 1 , wherein:
before forming the sacrificial layers, a portion of the spacers is also formed on the base substrate and on the top surface of each first gate structure;
a portion of the spacer on the top surface of each first gate structure is removed when forming the sacrificial layers; and
after forming the sacrificial layers, a portion of the spacer is located between the base substrate and the sacrificial layer.
8. The method according to claim 7 , wherein the spacer is formed by an atomic layer deposition process.
9. The method according to claim 7 , wherein:
a mask protection layer is formed on a top surface of each first gate structure;
before forming the sacrificial layers, a portion of the spacer is also formed on sidewalls and a top surface of each mask protection layer;
a portion of the spacer on the top surface of the mask protection layer is removed when forming the sacrificial layers;
the top surface of the mask protection layer is exposed after forming the sacrificial layers and before removing the first gate structures; and
the mask protection layer is removed after forming the bottom dielectric layer and before removing the first gate structures.
10. The method according to claim 7 , further including:
before removing the first gate structures, etching a partial height of each sacrificial layer to make a top surface of the sacrificial layer lower than a top surface of the bottom dielectric layer, and to form a third opening on each sacrificial layer between the bottom dielectric layer and the spacer;
forming a cap layer in each third opening;
removing the first gate structures; and
removing the cap layers when forming the second gate structures.
11. The method according to claim 10 , wherein the cap layers have a thickness of 20 nm to 50 nm.
12. The method according to claim 1 , wherein:
before forming the sacrificial layers, a portion of the spacer is further located on a top surface of each source/drain doped layer;
a portion of the sacrificial layer is located on each corresponding source/drain doped layer;
the sacrificial layers are removed to expose the spacer on the top surface of each source/drain doped layer;
a portion of the spacer on a bottom of each first opening is etched to expose the top surface of the corresponding source/drain doped layer, and to form a second opening on the bottom of each first opening; and
a plug is also located in the corresponding second opening.
13. The method according to claim 12 , before forming the plugs, further including:
forming a metal silicide layer on the top surface of each source/drain doped layer on the bottom of the corresponding first opening and the corresponding second opening.
14. The method according to claim 1 , wherein forming offset spacers on the sidewalls of each first gate structure is performed before forming the source/drain doped layers, wherein:
the source/drain doped layers are formed in the base substrate on the sidewalls of each first gate structure and of each offset spacer.
15. The method according to claim 14 , wherein the offset spacers are made of a material including SiNx.
16. The method according to claim 15 , wherein when removing the sacrificial layers by etching:
a ratio between an etching rate of the sacrificial layers and an etching rate of the spacer is 80:1 to 200:1; and
a ratio between the etching rate of the sacrificial layers and an etching rate of the bottom dielectric layer is 50:1 to 100:1.
17. A fabrication method for a semiconductor device, comprising:
forming a base substrate and first gate structures on the base substrate;
forming a spacer covering sidewalls of each first gate structure;
forming sacrificial layers on sidewalls of each first gate structure to cover corresponding spacers;
forming a bottom dielectric layer covering sidewalls of the sacrificial layers;
after forming the bottom dielectric layer, removing the sacrificial layers to form first openings between the bottom dielectric layer and the spacers; and
forming a plug in each first opening, after forming the bottom dielectric layer and before removing the sacrificial layers, further including:
removing the first gate structures to form gate openings in the bottom dielectric layer, wherein a portion of the spacer is located on the sidewalls of each gate opening;
forming a second gate structure in each gate opening; and
removing sacrificial layers.
18. The method according to claim 17 , wherein the spacer is made of a material including silicon oxide, silicon carbon nitride, or a combination thereof.
19. The method according to claim 17 , wherein the spacer has a dielectric constant of 2.5 to 3.7.
20. The method according to claim 17 , wherein the spacer has a thickness of 5 nm to 12 nm.
21. The method according to claim 17 , wherein the spacer has a thickness of 5 nm to 12 nm.