Semiconductor device including ultra low-k spacer and method for fabricating the same
A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.
1. A semiconductor device, comprising:
a bit line structure including a bit line contact plug and a bit line on the bit line contact plug;
a storage node contact plug;
an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line; and
a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug,
wherein the gap-fill spacer is thicker than the line-type spacer,
wherein the ultra low-k spacer includes a first carbon-doped spacer, and the low-k spacer includes a second carbon-doped spacer, and
wherein the first carbon-doped spacer has a lower carbon concentration than the second carbon-doped spacer.
2. The semiconductor device of claim 1 , wherein the ultra low-k spacer has a lower dielectric constant than the low-k spacer.
3. The semiconductor device of claim 1 , wherein the ultra low-k spacer has a lower dielectric constant than a silicon oxide (SiO 2 ), and the low-k spacer has a lower dielectric constant than a silicon nitride (Si 3 N 4 ).
4. The semiconductor device of claim 1 , wherein the ultra low-k spacer has a dielectric constant lower than 3.5, and the low-k spacer has a dielectric constant lower than 5.
5. The semiconductor device of claim 1 , wherein the gap-fill spacer and the line-type spacer includes the same ultra low-k material and are integrated.
6. The semiconductor device of claim 1 , wherein one gap-fill spacer is formed between the bit line contact plug and the storage node contact plug, and a bilayer of the line-type spacer and the low-k spacer is formed between the bit line and the storage node contact plug.
7. The semiconductor device of claim 1 , wherein the gap-fill spacer directly contacts the storage node contact plug.
8. The semiconductor device of claim 1 , wherein the ultra low-k spacer includes a silicon-based material including carbon.
9. The semiconductor device of claim 1 , wherein the low-k spacer includes a silicon-based material including carbon.
10. The semiconductor device of claim 1 , wherein the low-k spacer includes SiC, SiCN or SiBCN.
11. The semiconductor device of claim 1 , wherein the ultra low-k spacer includes first SiCO, the low-k spacer includes second SiCO, and a carbon concentration of the first SiCO is lower than a carbon concentration of the second SiCO.
12. The semiconductor device of claim 1 , wherein the line-type spacer of the ultra low-k spacer is thicker than the low-k spacer.
13. The semiconductor device of claim 1 , wherein the low-k spacer includes a material whose etch rate is lower than a silicon nitride.
14. The semiconductor device of claim 1 , further comprising:
a semiconductor substrate including a first impurity region coupled to the bit line contact plug and a second impurity region coupled to the storage node contact plug; and
a dielectric material formed on the semiconductor substrate and including a bit line contact hole that exposes the first impurity region,
wherein the bit line contact hole is filled with the bit line contact plug and the gap-fill spacer contacting both side walls of the bit line contact plug.
15. The semiconductor device of claim 14 , further comprising:
a trench formed between the first impurity region and the second impurity region;
a buried word line formed in the trench; and
a memory element formed on the storage node contact plug.
16. A semiconductor device, comprising:
a first pattern structure and a second pattern structure; and
a multilayer spacer separating the first and second pattern structures,
wherein the multilayer spacer includes an ultra low-k spacer contacting a side wall of the first pattern structure; and
a low-k spacer which is formed on the ultra low-k spacer and contacts the second pattern structure,
wherein the ultra low-k spacer includes a first carbon-doped spacer, and the low-k spacer includes a second carbon-doped spacer, and
wherein the first carbon-doped spacer has a lower carbon concentration than the second carbon-doped spacer.
17. The semiconductor device of claim 16 , wherein the ultra low-k spacer has a lower dielectric constant than the low-k spacer.
18. The semiconductor device of claim 16 , wherein the ultra low-k spacer has a lower dielectric constant than a silicon oxide (SiO 2 ), and the low-k spacer includes a lower dielectric constant than a silicon nitride (Si 3 N 4 ).
19. The semiconductor device of claim 16 , wherein the low-k spacer includes SiC, SiCN or SiBCN.
20. The semiconductor device of claim 16 , wherein the ultra low-k spacer includes first SiCO, the low-k spacer includes second SiCO, and a carbon concentration of the first SiCO is lower than a carbon concentration of the second SiCO.
21. The semiconductor device of claim 16 , wherein the first pattern structure includes a bit line, and the second pattern structure includes a storage node contact plug.
22. The semiconductor device of claim 16 , wherein the ultra low-k spacer is thicker than the low-k spacer.