Multi-gate device and method of fabrication thereof
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
1. A method of forming a semiconductor device, the method comprising:
providing a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the fin includes a first layer disposed over the substrate, a second layer disposed over the first layer, and a third layer disposed over the second layer;
removing at least a portion of the second layer from the channel region to form a gap between the first and third layers;
forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer;
depositing a second material in the channel region to form a high-k dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and
forming a metal layer along opposing sidewalls of the high-k dielectric layer the channel region.
2. The method of claim 1 , wherein each of the first and third layers has a rounded profile.
3. The method of claim 1 , wherein the metal layer includes a first material, and
wherein the gap is free of the first material.
4. The method of claim 3 , wherein the first material includes at least one of titanium, hafnium, zirconium, tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride, and titanium silicon nitride.
5. The method of claim 1 , further comprising:
forming the first layer by growing a first silicon germanium layer;
forming the second layer by growing a silicon layer directly on the first silicon germanium layer; and
forming the third layer by growing a second silicon germanium layer directly on the silicon layer.
6. The method of claim 1 , further comprising:
after the removing of the at least a portion of the second layer from the channel region, growing a silicon layer on the third layer.
7. The method of claim 1 , further comprising:
performing an annealing process to the metal layer to cause a scavenging process to the first and second interfacial layer portions.
8. A method, comprising:
forming a fin element including first, second, and third semiconductor layers;
removing at least a portion of the second semiconductor layer from a channel region of the fin element to form a gap between the first and third semiconductor layers;
forming an interposing feature in the channel region, wherein the interposing feature includes:
a first interfacial layer portion at least partially wrapping around the first semiconductor layer;
a second interfacial layer portion at least partially wrapping around the third semiconductor layer;
a dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and
depositing a metal layer at least partially wrapping around the interposing feature;
removing at least a portion of the second layer from the channel region to form a gap between the first and third layers;
forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the first layer and a second interfacial layer portion at least partially wrapping around the third layer;
depositing a second material in the channel region to form a high-k dielectric layer at least partially wrapping around the first interfacial layer portion and the second interfacial layer portion; and
forming a metal layer along opposing sidewalls of the high-k dielectric layer the channel region.
9. The method of claim 8 , wherein a thickness of the second semiconductor layer is less than twice of a width of a sidewall of the interposing feature.
10. The method of claim 9 , further comprising:
etching the first and third semiconductor layers so that each of the first and third semiconductor layers has a rounded profile.
11. The method of claim 10 , wherein the rounded profile is a rounded square, a circle, or an oval.
12. The method of claim 8 , wherein the metal layer includes a first material, and
wherein the gap is free of the first material.
13. The method of claim 8 , further comprising:
performing an annealing process to the metal layer to cause a scavenging process to the first and second interfacial layer portions.
14. The method of claim 13 , wherein all areas of the first and second interfacial layer portions are scavenged during the scavenging process.
15. A method, comprising:
providing a substrate including a fin element, the fin element including a bottom layer disposed over the substrate, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer;
forming a dummy gate structure in a channel region of the fin element;
forming a source/drain feature in a source/drain region of the fin element adjacent to the dummy gate structure;
removing the dummy gate structure to form an opening in the channel region to expose the fin element in the channel region;
removing at least a portion of the middle layer of the fin element exposed in the opening;
forming an interposing feature in the channel region, wherein the forming the interposing feature includes:
forming a first material in the channel region to form a first interfacial layer portion at least partially wrapping around the bottom layer and a second interfacial layer portion at least partially wrapping around the top layer;
forming a metal layer along opposing sidewalls of the interposing feature in the channel region, wherein the metal layer includes a scavenging material; and
causing a scavenging process to the first and second interfacial layer portions by performing an annealing process to the metal layer.
16. The method of claim 15 , further comprising:
after the removing of the at least a portion of the middle layer, etching the bottom and top layers in the channel region that each of the bottom and top layers has a rounded profile.
17. The method of claim 16 , further comprising:
after the etching of the bottom and top layers, growing a silicon layer on the bottom and top layers.
18. The method of claim 15 , wherein all areas of the first and second interfacial layer portions are scavenged during the scavenging process.
19. The method of claim 15 , wherein a thickness of the bottom layer is less than twice of a width of the interposing feature.
20. The method of claim 15 , wherein the bottom layer includes silicon germanium or germanium.