IP Library › Granted Patent US 10,840,432
Granted Patent B2
US 10,840,432 · App. 16/200,520 · Granted Nov 17, 2020

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Chia-Chang Hsu (Kaohsiung, TW); Chen-Yi Weng (New Taipei, TW); Chin-Yang Hsieh (Tainan, TW); Jing-Yin Jhang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/02G11C11/161H01F10/3254H01F41/34H01L27/222H01L43/12H01L43/10
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Quick Facts
Patent No.
US 10,840,432
App. No.
16/200,520
Granted
Nov 17, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Claims (18)

1. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises:

a bottom electrode layer, wherein the bottom electrode layer comprises a gradient concentration, the bottom electrode layer comprises tantalum nitride (TaN), a concentration of nitrogen increases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer, and a concentration of tantalum decreases from the bottom surface of the bottom electrode layer to the top surface of the bottom electrode layer;

a free layer on the bottom electrode layer; and

a top electrode layer on the free layer.

2. The semiconductor device of claim 1 , further comprising:

a pinned layer on the bottom electrode layer; and

a barrier layer on the pinned layer.

3. The semiconductor device of claim 1 , wherein a ratio of nitrogen to tantalum at a top surface of the bottom electrode layer is between 1.53 to 1.87.

4. The semiconductor device of claim 1 , wherein a ratio of nitrogen to tantalum at a bottom surface of the bottom electrode layer is between 0.18 to 0.22.

5. The semiconductor device of claim 1 , further comprising:

a metal interconnection under the MTJ;

an inter-metal dielectric (IMD) layer around the metal interconnection; and

an alignment mark adjacent to the metal interconnection.

6. The semiconductor device of claim 5 , wherein bottom surfaces of the metal interconnection and the alignment mark are coplanar.

7. The semiconductor device of claim 5 , wherein the alignment mark comprises:

a trench in the IMD layer; and

a spacer on sidewalls of the trench.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2018
From: WANG, HUI-LIN; HSU, CHIA-CHANG; WENG, CHEN-YI; HSIEH, CHIN-YANG; JHANG, JING-YIN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 047585/0312 →
Priority Claims (1)
CN 2018 1 1267036 · Oct 29, 2018 · national
Continuity (1)
Related Publication 20200136014A1 · Apr 30, 2020
Cited By (1)
US 12,290,005