Semiconductor device
An accumulation layer has a function of reducing an ON voltage (Von), which is a voltage between the collector and the emitter when turning on the IGBT, by accumulating carrier. However, when turning off the IGBT, the carrier contributes to a turn-off loss (Eoff). A semiconductor device is provided, comprising: a semiconductor substrate, wherein the semiconductor substrate includes: trench portions, a mesa portion each provided between two adjacent trench portions, and a drift layer, wherein the trench portions include: a gate trench portion, and a dummy trench portion, wherein the mesa portion has: an emitter region, a contact region, and a accumulation layer, wherein the number of accumulation layers provided in a depth direction in the mesa portion adjacent to the gate trench portion is larger than that of the accumulation layers provided in the depth direction in the mesa portion between the two dummy trench portions.
1. A semiconductor device comprising:
a semiconductor substrate including a transistor region,
wherein in the transistor region, the semiconductor substrate includes:
a plurality of trench portions extending in a predetermined direction,
a mesa portion each provided between two adjacent trench portions in the plurality of trench portions, and
a drift layer of a first conductivity type provided below the mesa portion,
wherein the plurality of trench portions include:
a gate trench portion having a gate conductive portion, to which a gate potential is supplied, and
a plurality of dummy trench portions, each having a dummy trench conductive portion, to which an emitter potential is supplied,
wherein the mesa portion comprises:
an emitter region of the first conductivity type having a higher doping concentration than the drift layer, the emitter region being at least partially positioned on an upper surface of the semiconductor substrate,
a contact region of a second conductivity type being at least partially positioned on an upper surface of the semiconductor substrate, and
one or more accumulation layers being provided below the emitter region and the contact region, the one or more accumulation layers having a higher doping concentration of the first conductivity type than the drift layer,
wherein a number of the one or more accumulation layers provided in a depth direction from the upper surface to a lower surface of the semiconductor substrate in the mesa portion adjacent to the gate trench portion is larger than the number of the one or more accumulation layers provided in the depth direction in the mesa portion between two dummy trench portions among the plurality of dummy trench portions.
2. The semiconductor device according to claim 1 , wherein
no accumulation layer is provided in the mesa portion between the two dummy trench portions.
3. The semiconductor device according to claim 1 , wherein
one accumulation layer is provided in the mesa portion between the two dummy trench portions.
4. The semiconductor device according to claim 1 , wherein
the emitter region and the contact region are alternately provided in the predetermined direction,
the mesa portion adjacent to the gate trench portion has a plurality of accumulation layers,
at least one accumulation layer among the plurality of accumulation layers is provided below at least a part of the emitter region, but is not provided below a partial region of the contact region.
5. The semiconductor device according to claim 4 , wherein
the at least one accumulation layer is an island-like accumulation layer including a plurality of accumulation regions having a higher doping concentration of the first conductivity type than the drift layer, the plurality of accumulation regions each provided in a discrete manner in a plane orthogonal to the depth direction,
each of the plurality of accumulation regions is provided below at least a part of the emitter region, but is not provided below a partial region of the contact region and is spaced apart,
all the accumulation layers other than the accumulation layer closest to the upper surface in the depth direction are the island-like accumulation layers.
6. The semiconductor device according to claim 5 , wherein
the mesa portion further has a base region having a lower doping concentration of the second conductivity type than the contact region,
the emitter region has a bottom region being, in the semiconductor substrate, not in direct contact with the contact region, and being in direct contact with the base region,
a length of each of the plurality of accumulation regions in the predetermined direction is longer than a length of the bottom region in the predetermined direction.
7. The semiconductor device according to claim 5 , wherein
the mesa portion further has a base region having a lower doping concentration of the second conductivity type than the contact region,
the emitter region has a bottom region being, in the semiconductor substrate, not in direct contact with the contact region, and being in direct contact with the base region,
a length of each of the plurality of accumulation regions in the predetermined direction is shorter than a length of the bottom region in the predetermined direction.
8. The semiconductor device according to claim 6 , wherein
when a length of each of the plurality of accumulation regions in the predetermined direction is L CHS , and a length of the bottom region in the predetermined direction of the emitter region is L 0 , the L CHS and the L 0 satisfy
0.5≤ L CHS /L 0 ≤2.
9. The semiconductor device according to claim 1 , wherein
in the transistor region, a first distance between the two dummy trench portions in a direction orthogonal to the predetermined direction is larger than a second distance between a dummy trench portion among the plurality of dummy trench portions and the gate trench portion in a direction orthogonal to the predetermined direction.