Semiconductor package having redistribution layer
A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.
1. A semiconductor package comprising:
a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity;
a first semiconductor chip in the cavity;
a plurality of conductive vias in the plurality of through holes, lower surfaces of the plurality of conductive vias being level with a lower surface of the silicon substrate and a lower surface of the first semiconductor chip;
a first redistribution layer on the silicon substrate, the first redistribution layer connected to the first semiconductor chip and the plurality of conductive vias, a lower surface of the first redistribution layer extending over upper surfaces of the plurality of conductive vias; and
a second redistribution layer below the silicon substrate, the second redistribution layer connected to the first semiconductor chip and the plurality of conductive vias.
2. The semiconductor package of claim 1 , further comprising:
a first encapsulant in the cavity, wherein
the first encapsulant is between an inner side surface of the cavity and a side surface of the first semiconductor chip.
3. The semiconductor package of claim 1 , wherein
an upper end of the first semiconductor chip and a lower end of the first semiconductor chip are respectively located at a same level as an upper end of the silicon substrate and a lower end of the silicon substrate.
4. The semiconductor package of claim 1 , wherein
the first semiconductor chip includes a through electrode, and
the through electrode passes through the first semiconductor chip in a vertical direction.
5. The semiconductor package of claim 1 , wherein the plurality of through holes surround the cavity.
6. The semiconductor package of claim 1 , further comprising:
a via insulating layer in each of the plurality of through holes to cover outer sides of the plurality of conductive vias.
7. The semiconductor package of claim 1 , wherein the plurality of through holes have a diameter of 2 to 50 μm.
8. The semiconductor package of claim 1 , further comprising:
a second semiconductor chip on the first redistribution layer, the second semiconductor chip connected to the first redistribution layer.
9. The semiconductor package of claim 8 , wherein the first semiconductor chip is configured to electrically connect to an external device via the second redistribution layer.
10. The semiconductor package of claim 8 , further comprising:
an external connecting member electrically connected to the second semiconductor chip via the first redistribution layer, the conductive vias, and the second redistribution layer.
11. The semiconductor package of claim 8 , wherein the first semiconductor chip is electrically connected to the second semiconductor chip via the first redistribution layer.
12. The semiconductor package of claim 8 , further comprising:
a plurality of second semiconductor chips on the first redistribution layer, wherein
the plurality of second semiconductor chips include the second semiconductor chip, and
the plurality of second semiconductor chips are electrically connected to each other via the first redistribution layer.
13. The semiconductor package of claim 8 , further comprising:
an upper pad on the first semiconductor chip;
a lower pad below the first semiconductor chip; and
a through electrode passing through the first semiconductor chip in a vertical direction,
wherein the upper pad and the lower pad are electrically connected to each other and connected via the through electrode.
14. The semiconductor package of claim 8 , wherein the plurality of through holes have a diameter of 2 to 50 μm.
15. The semiconductor package of claim 1 , further comprising:
a second semiconductor chip on the first redistribution layer, the second semiconductor chip connected to the first redistribution layer; and
a third semiconductor chip on the first semiconductor chip, the third semiconductor chip connected to the first redistribution layer.
16. The semiconductor package of claim 15 , wherein the first semiconductor chip is electrically connected to the first redistribution layer via the third semiconductor chip.
17. The semiconductor package of claim 15 , wherein the third semiconductor chip is electrically connected to the second redistribution layer via the first semiconductor chip.
18. The semiconductor package of claim 15 , wherein the second semiconductor chip is electrically connected to the first semiconductor chip via the first redistribution layer and the third semiconductor chip.
19. The semiconductor package of claim 1 , wherein an upper surface of the second redistribution layer extends below the lower surfaces of the plurality of conductive vias.
20. A semiconductor package comprising:
a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity;
a first semiconductor chip in the cavity;
a plurality of conductive vias in the plurality of through holes;
a first redistribution layer on the silicon substrate, the first redistribution layer connected to the first semiconductor chip and the plurality of conductive vias; and
a second redistribution layer below the silicon substrate, the second redistribution layer connected to the first semiconductor chip and the plurality of conductive vias;
a first encapsulant in the cavity, the first encapsulant being between an inner side surface of the cavity and a side surface of the first semiconductor chip; and
an adhesive in the cavity, wherein
the adhesive is between the first encapsulant and the second redistribution layer.