Etch profile control of interconnect structures
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
1. An integrated circuit, comprising:
a substrate;
a dielectric disposed on the substrate and comprising contact structures, wherein top surfaces of the contact structures are coplanar with a top surface of the dielectric; and
an interconnect structure electrically coupled to the contact structures, the interconnect structure comprising:
an etch stop layer, with a homogeneous composition, positioned on and in contact with the top surface of the dielectric;
a carbide liner positioned on and in contact with a top surface of the etch stop layer; and
a metal nitride layer positioned on and in contact with a top surface of the carbide liner, wherein an entire portion of the metal nitride layer is above the top surface of the carbide liner;
an interlayer dielectric (ILD) layer positioned on the metal nitride layer; and
a conductive via traversing through the ILD layer, the metal nitride layer, the carbide liner, and the etch stop layer.
2. The integrated circuit of claim 1 , further comprising a metal oxide layer interposed between the ILD layer and the metal nitride layer.
3. The integrated circuit of claim 1 , wherein the carbide liner comprises oxygen-doped carbide.
4. The integrated circuit of claim 1 , wherein the carbide liner has a thickness between about 3 nm and about 8 nm.
5. The integrated circuit of claim 1 , wherein a sidewall of the conductive via forms an angle with a horizontal axis in a range from about 70° to about 80°.
6. The integrated circuit of claim 1 , wherein each of the etch stop layer, the carbide liner, and the metal nitride layer is parallel to the top surfaces of the contact structures.
7. The integrated circuit of claim 1 , wherein the metal nitride layer comprises chromium, aluminum, titanium, tin, zinc, magnesium, silver, nickel, molybdenum, and combinations thereof.
8. An interconnect structure, comprising:
first conductive structures embedded in a first dielectric over a substrate;
an etch stop layer disposed on and in contact with a top surface of the first dielectric;
a liner disposed on and in contact with a top surface of the etch stop layer;
a metal carbide layer disposed on and in contact with a top surface of the liner, wherein an entire portion of the metal carbide layer is above the top surface of the liner;
a metal oxide layer disposed on the metal carbide layer;
a second dielectric disposed on the metal oxide layer;
second conductive structures in physical contact with the first conductive structures and partially within the second dielectric, the metal oxide layer, the metal carbide layer, the liner, and the etch stop layer; and
third conductive structures embedded in the second dielectric and in physical contact with the second conductive structures.
9. The interconnect structure of claim 8 , further comprising:
fourth conductive structures embedded in the second dielectric not in physical contact with the second conductive structures.
10. The interconnect structure of claim 8 , wherein a ratio of a top width to a bottom width of each of the second conductive structures is between about 2 and about 3.
11. The interconnect structure of claim 8 , wherein the liner has a thickness between about 3 nm and about 8 nm.
12. The interconnect structure of claim 8 , wherein the first conductive structures comprise a conductive material different from that of the second conductive structures.
13. The interconnect structure of claim 8 , wherein the metal carbide layer comprises chromium, aluminum, titanium, tin, zinc, magnesium, silver, nickel, molybdenum, and combinations thereof.
14. An integrated circuit, comprising:
a dielectric layer over a substrate, wherein the dielectric layer comprises first conductive structures formed therein;
an interconnect layer disposed on the dielectric layer, wherein the interconnect layer comprises:
a stack comprising:
a metal oxide layer disposed on and in contact with top surfaces of the dielectric layer;
a metal nitride layer disposed on and in contact with top surfaces of the metal oxide layer; and
a metal carbide layer disposed on and in contact with top surfaces of the metal nitride layer;
second conductive structures in physical contact with the first conductive structures; and
third conductive structures in physical contact with the second conductive structures.
15. The integrated circuit of claim 14 , further comprising:
an etch stop layer disposed on the dielectric layer and below the stack;
a liner interposed between the etch stop layer and the stack; and
an other dielectric over the stack, wherein the second conductive structures are partially surrounded by the other dielectric, the stack, the liner, and the etch stop layer.
16. The integrated circuit of claim 14 , wherein the third conductive structures are surrounded by the other dielectric.
17. The integrated circuit of claim 15 , wherein the liner comprises an oxygen-doped material with a thickness between about 3 nm and about 8 nm.
18. The integrated circuit of claim 14 , wherein a top width of each of the second conductive structures is between about 2 and about 3 times wider than a bottom width of each of the second conductive structures.
19. The integrated circuit of claim 14 , wherein the second conductive structures have substantially vertical sidewalls with a sidewall angle between about 70° and about 80°.
20. The integrated circuit of claim 14 , wherein each of the metal oxide layer, the metal nitride layer, and the metal carbide layer comprises chromium, aluminum, titanium, tin, zinc, magnesium, silver, nickel, molybdenum, and combinations thereof.