IP Library Granted Patent US 11,145,689
Granted Patent B2
US 11,145,689 · App. 16/203,709 · Granted Oct 12, 2021

Indicia for light emitting diode chips

Inventors: Nikolas Hall (Durham, NC); Derek Miller (Holly Springs, NC); Anoop Mathew (Morrisville, NC); Colin Blakely (Franklinton, NC); Luis Breva (Morrisville, NC); Jesse Reiherzer (Raleigh, NC); David Todd Emerson (Chapel Hill, NC)
Assignee: CreeLED, Inc.
H01L27/156H01L23/544H01L33/005H01L33/22H01L33/60H01L33/62H01L2223/5442H01L2223/54406H01L2223/54426H01L2223/54433H01L2933/0066
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Quick Facts
Patent No.
US 11,145,689
App. No.
16/203,709
Granted
Oct 12, 2021
Kind
B2
Abstract

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips and related methods are disclosed. LED chips are provided that include an indicia arranged between a primary light-emitting face and a mounting face of the LED chip. The indicia may include at least one of a logo, one or more alphanumeric characters, or a symbol, among others that are configured to convey information. Arrangements of at least one of an n-contact, a p-contact, or a reflector layer of the LED chip may form the indicia. LED chips are also provided where at least a portion of an indicia is arranged on a mounting face of the LED chip. Indicia are provided that may be visible through primary light-emitting faces when LED chips are electrically activated or electrically deactivated. In this regard, the indicia may be embedded within LED chips while still being able to convey information.

Claims (29)

1. A light emitting diode (LED) chip, comprising:

a mounting face configured to be mounted to a surface;

a primary light-emitting face that is opposite the mounting face;

an active LED structure arranged between the mounting face and the primary light-emitting face, wherein the active LED structure comprises an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer; and

an indicia arranged between the mounting face and the primary light-emitting face, wherein the indicia extends through an opening in the p-type layer and the active layer and a continuous portion of the opening is elongated across the primary light-emitting face to form an outline of the indicia, and wherein a portion of the p-type layer and the active layer are bounded within the outline of the indicia.

2. The LED chip of claim 1 , wherein the indicia comprises at least one of a logo, one or more alphanumeric characters, a symbol, an alignment marker, a fiducial marker, or a polarity marker configured to convey information.

3. The LED chip of claim 1 , wherein the indicia is arranged closer to the mounting face than the primary light-emitting face.

4. The LED chip of claim 1 , further comprising an n-contact electrically connected to the n-type layer, wherein a portion of the n-contact forms the indicia.

5. The LED chip of claim 4 , wherein the n-contact comprises one or more n-contact interconnects that extend through a portion of the active LED structure to the n-type layer.

6. The LED chip of claim 5 , wherein the one or more n-contact interconnects form the indicia.

7. The LED chip of claim 5 , wherein the one or more n-contact interconnects form the outline of the indicia.

8. The LED chip of claim 7 , wherein the portion of the active LED structure that is bounded by the outline is continuous with other portions of the active LED structure that are not bounded by the outline.

9. The LED chip of claim 1 , further comprising a reflective structure on the p-type layer, wherein a portion of the reflective structure forms the indicia.

10. The LED chip of claim 9 , wherein the reflective structure comprises a metal layer, a dielectric layer, and one or more reflective layer interconnects that extend through a portion of the dielectric layer.

11. The LED chip of claim 10 , wherein the one or more reflective layer interconnects form the indicia.

12. The LED chip of claim 9 , wherein a pattern of the reflective structure forms the indicia.

13. The LED chip of claim 1 further comprising:

an n-contact electrically connected to the n-type layer, wherein a portion of the n-contact forms the indicia; and

a reflector layer on the p-type layer wherein a portion of the reflector layer forms another indicia.

14. The LED chip of claim 1 , further comprising a growth substrate, wherein a portion of the growth substrate forms the primary light-emitting face.

15. A light emitting diode (LED) chip, comprising:

a mounting face configured to be mounted to a surface;

a primary light-emitting face that is opposite the mounting face;

an active LED structure arranged between the mounting face and the primary light-emitting face, wherein the active LED structure comprises an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer;

a passivation layer on the p-type layer; and

a p-contact electrically connected to the p-type layer, wherein the p-contact comprises a portion that is on the mounting face and a plurality of p-contact interconnects that extend through the passivation layer, wherein individual ones of the plurality of the p-contact interconnects extend through the passivation layer with different shapes from one another and the plurality of p-contact interconnects are grouped together to form at least a portion of an indicia arranged on the mounting face.

16. The LED chip of claim 15 , wherein the p-contact and the plurality of the p-contact interconnects form the indicia.

17. The LED chip of claim 15 , wherein the portion of the p-contact that is on the mounting face forms another portion of the indicia.

18. The LED chip of claim 15 , wherein the indicia comprises at least one of a logo, one or more alphanumeric characters, a symbol, an alignment marker, a fiducial marker, or a polarity marker configured to convey information.

Assignments (5)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 058983/0001 Recorded Jun 25, 2025
From: CITIZENS BANK, N.A.
To: SMART MODULAR TECHNOLOGIES, INC.; SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; CREELED, INC.
Reel/Frame 071725/0207 →
SECURITY INTEREST Recorded Feb 7, 2022
From: SMART MODULAR TECHNOLOGIES, INC.; SMART HIGH RELIABILITY SOLUTIONS, LLC; SMART EMBEDDED COMPUTING, INC.; CREELED, INC.
To: CITIZENS BANK, N.A.
Reel/Frame 058983/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2021
From: CREE, INC.
To: CREELED, INC.
Reel/Frame 056780/0580 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: HALL, NIKOLAS; MILLER, DEREK; MATHEW, ANOOP; BLAKELY, COLIN; BREVA, LUIS; REIHERZER, JESSE; EMERSON, DAVID TODD
To: CREE, INC.
Reel/Frame 048236/0393 →
Continuity (1)
Related Publication 20200176507A1 · Jun 4, 2020