Packaging method and package structure of wafer-level system-in-package

1. A wafer-level system-in-package (WLSiP) packaging method, comprising:

providing a device wafer, wherein the device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface;

providing a plurality of second chips;

forming an adhesive layer capable of photolithography on the first front surface of the device wafer;

patterning the adhesive layer to form a plurality of first through-holes in the adhesive layer, exposing the first front surface;

after patterning the adhesive layer, bonding the plurality of second chips with a remaining adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence;

forming a plurality of second through-holes passing through the device wafer by etching the first back surface of the device wafer, wherein the plurality of second through-holes are connected with the plurality of first through-holes to form a plurality of first conductive through-holes, each first conductive through-hole includes a second through-hole and a first through-hole; and

forming a first conductive plug in each first conductive through-hole to electrically connect to one of the plurality of second chips.

2. The method according to claim 1 , after bonding the plurality of second chips with the remaining adhesive layer and before etching the first back surface of the device wafer, further including:

forming an encapsulation layer on the first front surface to cover the plurality of second chips; and

thinning the device wafer through the first back surface.

3. The method according to claim 1 , after bonding the plurality of second chips with the remaining adhesive layer and before forming the first conductive plug in the first conductive through-hole to electrically connect to the one of the plurality of second chips, further including:

forming a second conductive through-hole to expose the first chip in the device wafer by etching the first back surface of the device wafer; and

when forming the first conductive plug, forming a second conductive plug in the second conductive through-hole to electrically connect to the first chip.

4. The method according to claim 3 , after forming the first conductive plug and the second conductive plug, further including:

forming a first bonding pad and a second bonding pad on the first back surface of the device wafer to cover the first conductive plug and the second conductive plug, respectively;

forming a passivation layer on the first back surface to cover tops of the first and second bonding pads; and

patterning the passivation layer to expose a portion of each of the first and second bonding pads.

5. The method according to claim 1 , wherein:

the second chip includes a second front surface having semiconductor devices formed thereon and a second back surface opposing the second front surface; and

one of the second front surface and the second back surface is bonded with the remaining adhesive layer.

6. The method according to claim 1 , wherein, after patterning the adhesive layer,

the remaining adhesive layer exposes the first front surface at a location corresponding to the first through-hole.

7. The method according to claim 1 , wherein:

the adhesive layer is made of one of a dry film, polyimide, polybenzoxazole, and benzocyclobutene.

8. The method according to claim 1 , wherein patterning the adhesive layer includes:

performing exposure and development processes on the adhesive layer.

9. The method according to claim 1 , wherein:

a process of etching the device wafer includes one or more of a dry etching and a wet etching.

10. The method according to claim 1 , wherein:

the plurality of second chips have at least one type of function.

11. The method according to claim 1 , wherein, after patterning the adhesive layer,

the remaining adhesive layer covers the first front surface at a location corresponding to the second chip.