Copper passivation
In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 μm on a surface of the copper corrosion inhibitor layer.
1. An assembly, comprising:
copper structures on a substrate;
a copper corrosion inhibitor layer coating at least portions of the copper structures; and
a protection layer less than 35 μm thick coating the copper corrosion inhibitor layer.
2. The assembly of claim 1 , wherein the copper corrosion inhibitor layer further comprises an azole.
3. The assembly of claim 2 , wherein the copper corrosion inhibitor layer further comprises benzotriazole (BTA).
4. The assembly of claim 1 , wherein the copper corrosion inhibitor layer further comprises one selected from a group consisting essentially of: an azole, benzotriazole (BTA), N-phenyl-1 4-phenylenediamine (NPPD), amino acids, cysteine, valine, glycine, arginine, lysine, triphenylmethane, rosaniline chloride, fuchsin acid sodium salt; thiole groups, phosphate groups, triethyl phosphate, triphenyl phosphate, and derivatives and combinations thereof.
5. The assembly of claim 1 , wherein the substrate is one selected from a group consisting essentially of: a film-based substrate carrying conductors; a ceramic substrate, a laminate substrate with multiple layers of conductors and insulators; a lead frame, a semiconductor substrate, and a printed circuit board substrate.
6. The assembly of claim 1 , wherein the assembly is a semiconductor die and wherein the semiconductor die is covered with a packaging protection layer.
7. The assembly of claim 1 , wherein the assembly is a semiconductor die.
8. The assembly of claim 1 , wherein the assembly is a semiconductor die and wherein the semiconductor die is mounted on the substrate that is a lead frame and the semiconductor die and the lead frame are at least partially covered with mold compound.
9. The assembly of claim 1 , wherein the assembly is a printed circuit board.
10. The assembly of claim 1 , wherein the protection layer is a polymer that is one selected from a group consisting essentially of: a polyimide, an epoxy-based polymer, a silicone, and a UV-curable acrylate polymer.
11. The assembly of claim 1 , wherein the protection layer is ink jet deposited and has a convex sidewall.
12. The assembly of claim 1 , wherein the protection layer has a sidewall that is straight and within 20 degrees of vertical, indicative of screen-print deposition or of and slit print deposition.
13. The assembly of claim 1 , wherein the copper corrosion inhibitor layer is a BTA layer with a molecular weight in a range from 119 g/mole to about 200 g/mole.
14. The assembly of claim 1 , wherein the copper corrosion inhibitor layer is a BTA layer that is stable to a temperature of about 260° C.
15. The assembly of claim 1 , wherein the protection layer has a modulus less than 3.4 GPa.
16. The assembly of claim 1 , wherein the protection layer has a thickness between 2 μm and 20 μm.
17. The assembly of claim 1 , wherein the protection layer has a thickness between 2 μm and 10 μm.
18. A packaged semiconductor device, comprising:
a semiconductor die mounted on a substrate;
copper structures on the semiconductor die at least partially coated with a copper corrosion inhibitor layer;
a protection layer less than 35 μm thick coating the copper corrosion inhibitor layer; and
the semiconductor die, the protection layer, and at least a portion of the substrate coated with mold compound.
19. The packaged semiconductor device of claim 18 , wherein the substrate is one selected from a group consisting essentially of: a lead frame, a film-based substrate carrying conductors; a ceramic substrate, a laminate substrate with multiple layers of conductors and insulators; a fiberglass substrate, an FR4 substrate, a semiconductor substrate, a tape-based substrate, a pre-molded lead frame, a molded interconnect substrate, and a printed circuit board.
20. The packaged semiconductor device of claim 18 , wherein the semiconductor die is mounted on a lead frame, and the semiconductor die and a portion of the lead frame are covered with mold compound.
21. The packaged semiconductor device of claim 18 , wherein the protection layer is a polymer that is one selected from a group consisting essentially of: a polyimide, an epoxy-based polymer, a silicone, and a UV-curable acrylate polymer.
22. The packaged semiconductor device of claim 18 , wherein the protection layer is ink jet deposited and a sidewall on the protection layer has a convex shape.
23. The packaged semiconductor device of claim 18 , wherein a sidewall on the protection layer is straight and within 20 degrees of vertical.
24. The packaged semiconductor device of claim 18 , wherein the copper corrosion inhibitor layer is an azole.
25. The packaged semiconductor device of claim 24 , wherein the azole of the copper corrosion inhibitor layer is BTA that has a molecular weight greater than about 119 g/mole.
26. The packaged semiconductor device of claim 18 , wherein the copper corrosion inhibitor layer is stable to a temperature of about 260° C.
27. A semiconductor device, comprising:
a wafer including a plurality of semiconductor dies spaced from one another, each semiconductor die having a copper structure on a circuit side surface,
a copper corrosion inhibitor layer over the copper structure; and
a protective layer over the copper corrosion inhibitor layer having a thickness less than 35 μm thick.
28. The semiconductor device of claim 27 , wherein the protection layer is a polymer that is one selected from a group consisting essentially of: a polyimide, an epoxy-based polymer, a silicone, and a UV-curable acrylate polymer.
29. The semiconductor device of claim 27 , wherein the protection layer is ink jet deposited and a sidewall on the protection layer has a convex shape.
30. The semiconductor device of claim 27 , wherein a sidewall on the protection layer is straight and within 20 degrees of vertical.
31. The semiconductor device of claim 27 , wherein the copper corrosion inhibitor layer is one selected from a group consisting essentially of: an azole, benzotriazole (BTA), N-phenyl-1, 4-phenylenediamine (NPPD), amino acids, cysteine, valine, glycine, arginine, lysine, triphenylmethane, rosaniline chloride, acid fuchsin sodium salt; thiole groups, phosphate groups, triethyl phosphate, triphenyl phosphate, and derivatives and combinations thereof.
32. The semiconductor device of claim 27 , wherein the protection layer has a modulus less than 3.4 GPa.
33. A method for passivating a copper structure, comprising:
passivating a surface of a copper structure on a substrate with a copper corrosion inhibitor layer; and
depositing a protection overcoat layer with a thickness less than 35 μm over a surface of the copper corrosion inhibitor layer.
34. The method of claim 33 , further comprising depositing the protection overcoat layer using ink-jet deposition.
35. The method of claim 33 , further comprising depositing the protection overcoat layer using one selected from screen print deposition and slit print deposition.
36. The method of claim 33 , further comprising depositing the protection overcoat layer with the thickness between 2 μm and 20 μm.
37. The method of claim 33 , further comprising depositing the protection overcoat layer that is one selected from a group consisting essentially of: polyimide; a thermally curable epoxy-based polymer; a UV-curable acrylate polymer; and a silicone.
38. The method of claim 33 further comprising depositing the protection overcoat layer wherein the protection overcoat layer has a modulus less than 3.4 GPa.