Semiconductor device package with isolated semiconductor die and electric field curtailment
In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.
1. A semiconductor package comprising:
a lead frame including a first portion and a second portion spaced from and electrically isolated from the first portion, the first portion including a planar device side surface and a planar opposite surface, and a side surface with a first side portion normal to the planar opposite and a second side portion at an angle with respect to the first side portion;
a spacer dielectric mounted to the planar device side surface of the first portion of the lead frame;
a semiconductor die mounted to the spacer dielectric;
the second portion of the lead frame comprising leads coupled to the bond pads of the semiconductor die by electrical connections; and
mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion of the lead frame and partially covering the second portion of the lead frame.
2. The semiconductor package of claim 1 , wherein the semiconductor die is electrically isolated from the first portion of the lead frame.
3. The semiconductor package of claim 1 , wherein the semiconductor die further comprises a current sensor that is configured to output a signal in response to a magnetic field in the first portion of the lead frame.
4. The semiconductor package of claim 3 , wherein the current sensor comprises a Hall element formed in the semiconductor die.
5. The semiconductor package of claim 4 , wherein the Hall element on the semiconductor die is configured to receive a magnetic field due to a current flowing in the current sense portion.
6. The semiconductor package of claim 3 , wherein the current sense portion of the first portion of the lead frame is positioned over a portion of the semiconductor die.
7. The semiconductor package of claim 1 , wherein the first portion of the lead frame further comprises a current sense portion that is positioned over a portion of the semiconductor die.
8. The semiconductor package of claim 1 , wherein the angle of the second side portion of the side surface is between 30 and 60 degrees with respect to the planar device side surface.
9. The semiconductor package of claim 1 , wherein the semiconductor die is partially covered by the spacer dielectric, the semiconductor die includes bond pads formed on a surface of the semiconductor die that extends beyond an edge of the spacer dielectric.
10. The semiconductor package of claim 1 , wherein the spacer dielectric is flame retardant 4 (FR4), glass reinforced epoxy, bismaleimide triazine (BT) resin, ceramic, tape or film.
11. The semiconductor package of 1 , wherein the semiconductor die has notched edges.
12. The semiconductor package of claim 1 , wherein parts of the first and second leads of the first portion, and parts of the leads of the second portion, are exposed from the mold compound, and the mold compound forms a body of a semiconductor device package.
13. The semiconductor package of claim 1 , wherein the lead frame is one selected from copper, gold, alloy 42 , stainless steel, steel, or alloys thereof.
14. The semiconductor package of claim 1 , wherein the spacer dielectric is mounted to the planar device side surface of the first portion of the lead frame by first die attach material and the semiconductor die is mounted to the second surface of the spacer dielectric by second die attach material.
15. The semiconductor package of claim 1 , wherein the second side portion is recessed with respect to the first side portion.