Resistive memory arrays for performing multiply-accumulate operations

1. A resistive memory array comprising:

a number of memristors to receive a common-valued read signal that has a voltage less than a switching voltage of the number of memristors, in which a resistance of a memristor defines a value within a matrix;

a number of multiplication engines to perform a multiply operation by:

receiving a memristor output from a corresponding memristor;

receiving an input signal; and

generating a multiplication output based on a received memristor output and a received input signal; and

an accumulation engine to sum multiplication outputs from the number of multiplication engines, in which summed multiplication outputs represent a multiplication of the matrix and a number of input signals.

2. The resistive memory array of claim 1 , in which the voltage of the common-valued read signal is a largest voltage less than the switching voltage of the number of memristors.

3. The resistive memory array of claim 1 , in which the voltage of the common-valued read signal is to allow for an improved signal-to-noise ratio for currents from the memristors.

4. The resistive memory array of claim 1 , in which the number of multiplication engines comprise a voltage-to-resistance converter to convert an input voltage signal into an input resistance.

5. The resistive memory array of claim 1 , in which the number of multiplication engines comprise a current-to-resistance converter to convert an input current signal into an input resistance.

6. The resistive memory array of claim 1 , in which each of the number of multiplication engines is respectively coupled to a corresponding one of the number of memristors.

7. The resistive memory array of claim 1 , in which each multiplication engine comprises an operational amplifier to amplify the memristor output from the corresponding memristor.

8. The resistive memory array of claim 1 , in which each multiplication engine comprises a current mirror multiplier circuit to amplify the memristor output from the corresponding memristor.

9. A method for performing a multiply-accumulate operation, the method comprising:

applying a common-valued read signal to inputs of a number of memristors, in which the common-valued read signal is a voltage less than a switching voltage of the number of memristors;

applying a number of input signals to a number of multiplication engines, in which a multiplication engine is coupled to a memristor;

summing a number of multiplication outputs from the number of multiplication engines, in which a multiplication output represents a multiplication of an memristor output and an input signal; and

determining an array output based on a summed number of the multiplication outputs.

10. The method of claim 9 , in which the voltage of the common-valued read signal is a largest voltage less than the switching voltage of the number of memristors.

11. The method of claim 9 , in which:

the memristor output comprises a current;

the number of input signals comprises a number of input voltages;

the number of multiplication outputs comprise a number of multiplication output voltages; and

the array output comprises an array output voltage.

12. The method of claim 11 , in which the voltage of the common-valued read signal is selected to improve the signal-to-noise ratio for the currents from the memristors.

13. The method of claim 9 , in which:

applying a number of input signals to a number of multiplication engines comprises applying a vector input signal to the number of multiplication engines; and

an entry in the vector input signal is directed to a different multiplication engine.

14. A computing device comprising:

a processor; and

a resistive memory array coupled to the processor, the resistive memory array comprising:

a number of resistive memory elements to receive a common-valued read voltage, in which a resistance of a resistive memory element defines a value within a matrix;

a number of multiplication engines to perform a multiplication operation, in which each multiplication engine:

is respectively coupled to a resistive memory element;

is to receive a resistive memory element output current;

is to output a multiplication current;

comprises a current mirror multiplier circuit to amplify the resistive memory element output current; and

comprises an input converter to convert a received input voltage into a resistance, in which the received input voltage represents an input signal to be multiplied by the matrix;

a conditioning resistor to condition a number of the output multiplication currents; and

an accumulation engine to sum a number of multiplication currents to generate an array output voltage.

15. The computer device of claim 14 , in which the common-valued read voltage is less than a switching voltage of the number of resistive memory elements.

16. The computing device of claim 14 , in which the common-valued read voltage is to improve the signal-to-noise ratio for the resistive memory element output current.

17. The computing device of claim 14 , in which the number of resistive memory elements are memristors.

18. The computing device of claim 14 , in which the resistive memory array is a resistive crossbar array comprising:

a number of row lines; and

a number of column lines intersecting the row lines to form a number of junctions;

in which the number of resistive memory element are coupled between the row lines and the column lines at the junctions.

19. The computing device of claim 14 , in which the input converter is a voltage-controlled resistor (VCR).

20. The computing device of claim 14 , in which the input converter is a metal-oxide semiconductor field-effect transistor (MOSFET).