Method of forming a heterojunction semiconductor device having integrated clamping device
A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
1. A cascode switch structure, comprising:
a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode;
a semiconductor MOSFET device having a third current carrying electrode electrically coupled to the first current carrying electrode, a fourth current carrying electrode electrically coupled to the first control electrode, and a second control electrode;
a first diode having a first cathode electrode electrically coupled to the second current carrying electrode and a first anode electrode; and
a second diode having a second anode electrode electrically coupled to the first anode electrode and a second cathode electrode electrically coupled to the fourth current carrying electrode.
2. The cascode switch structure of claim 1 , wherein:
the second current carrying electrode is configured to receive a peak negative voltage for the cascode switch structure; and
the second diode is configured to have a breakdown voltage greater than the peak negative voltage.
3. The cascode switch structure of claim 1 , wherein the first diode has a greater breakdown voltage than that of the second diode.
4. The cascode switch structure of claim 1 , wherein the second diode has a smaller capacitance than that of the first diode.
5. The cascode switch structure of claim 1 , wherein:
the group III-V transistor structure, the first diode, and the second diode comprise an integrated structure comprising:
a semiconductor substrate having a first major surface and an opposing second major surface;
a heterostructure adjacent the first major surface, the heterostructure comprising:
a channel layer; and
a barrier layer over the channel layer;
the first current carrying electrode disposed proximate to a first portion of the channel layer;
the second current carrying electrode disposed proximate to a second portion of the channel layer and spaced apart from the first current carrying electrode, wherein the second current carrying electrode is electrically decoupled from the semiconductor substrate;
the first control electrode disposed between the first current carrying electrode and the second current carrying electrode and configured to control a first current path between the first current carrying electrode and the second current carrying electrode;
a conductive electrode disposed on the second major surface of the semiconductor substrate;
a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the second current carrying electrode;
a first doped region of a first conductivity type disposed in the semiconductor substrate adjacent the first trench electrode;
a second doped region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor substrate between the second major surface and the first doped region;
a first semiconductor region disposed between the first doped region and the second doped region; and
a third doped region of the first conductivity type disposed between the second major surface and the second doped region;
the first diode includes the first doped region, the first semiconductor region and the second doped region; and
the second diode includes the second doped region and the third doped region.
6. The cascode switch structure of claim 5 , wherein:
the first doped region comprises an n-type region having an n−/n/n+/n/n− dopant profile with the n+ portion of the n−/n/n+/n/n− dopant profile adjoining the first trench electrode;
the second doped region comprises a p-type region; and
the third doped region comprises an n-type region having an n+/n/n− dopant profile with the n+ portion of the n+/n/n− dopant profile adjoining the second major surface.
7. The cascode switch structure of claim 6 , wherein the first semiconductor region comprises one of an intrinsic region or a p-type doped region.
8. The cascode switch structure of claim 5 , further comprising:
a second semiconductor region disposed between the first doped region and the heterostructure; and
a fourth doped region of the second conductivity type disposed between the second semiconductor region and the heterostructure, wherein:
the first doped region, the second semiconductor region, and the fourth doped region define a third diode; and
the third diode is configured to have a higher breakdown voltage than the first diode.
9. The cascode switch structure of claim 8 , further comprising:
a second trench electrode extending through the heterostructure into the semiconductor substrate and terminating within the fourth doped region; and
a fifth doped region of the first conductive type disposed within the fourth doped region and adjoining the second trench electrode, wherein:
the fifth doped region and the fourth doped region define a fourth diode; and
the second trench electrode is electrically coupled to the first control electrode.
10. A cascode switch structure, comprising:
a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode;
a semiconductor MOSFET device having a third current carrying electrode electrically coupled to the first current carrying electrode, a fourth current carrying electrode electrically coupled to the first control electrode, and a second control electrode;
a first diode having a first cathode electrode electrically coupled to the second current carrying electrode and a first anode electrode; and
a second diode having a second anode electrode electrically coupled to the first anode electrode and a second cathode electrode electrically coupled to the fourth current carrying electrode, wherein the first diode has a greater breakdown voltage than that of the second diode.
11. The cascode switch structure of claim 10 , wherein:
the second current carrying electrode is configured to receive a peak negative voltage for the cascode switch structure;
the second diode is configured to have a breakdown voltage greater than the peak negative voltage; and
the second diode has a smaller capacitance than that of the first diode.
12. The cascode switch structure of claim 10 , wherein:
the group III-V transistor structure, the first diode, and the second diode comprise an integrated structure comprising:
a semiconductor substrate having a first major surface and an opposing second major surface;
a heterostructure adjacent the first major surface, the heterostructure comprising:
a channel layer; and
a barrier layer over the channel layer;
the first current carrying electrode disposed proximate to a first portion of the channel layer;
the second current carrying electrode disposed proximate to a second portion of the channel layer and spaced apart from the first current carrying electrode, wherein the second current carrying electrode is electrically decoupled from the semiconductor substrate;
the first control electrode disposed between the first current carrying electrode and the second current carrying electrode and configured to control a first current path between the first current carrying electrode and the second current carrying electrode;
a conductive electrode disposed on the second major surface of the semiconductor substrate;
a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the second current carrying electrode;
a first doped region of a first conductivity type disposed in the semiconductor substrate adjacent the first trench electrode;
a second doped region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor substrate between the second major surface and the first doped region;
a first semiconductor region disposed between the first doped region and the second doped region; and
a third doped region of the first conductivity type disposed between the second major surface and the second doped region;
the first diode includes the first doped region, the first semiconductor region and the second doped region; and
the second diode includes the second doped region and the third doped region.
13. The cascode switch structure of claim 12 , wherein:
the first doped region comprises an n-type region having an n−/n/n+/n/n− dopant profile with the n+ portion of the n−/n/n+/n/n− dopant profile adjoining the first trench electrode;
the second doped region comprises a p-type region; and
the third doped region comprises an n-type region having an n+/n/n− dopant profile with the n+ portion of the n+/n/n− dopant profile adjoining the second major surface.
14. The cascode switch structure of claim 13 , wherein the first semiconductor region comprises one of an intrinsic region or a p-type doped region.
15. The cascode switch structure of claim 12 , further comprising:
a second semiconductor region disposed between the first doped region and the heterostructure; and
a fourth doped region of the second conductivity type disposed between the second semiconductor region and the heterostructure, wherein:
the first doped region, the second semiconductor region, and the fourth doped region define a third diode; and
the third diode is configured to have a higher breakdown voltage than the first diode.
16. The cascode switch structure of claim 15 , further comprising:
a second trench electrode extending through the heterostructure into the semiconductor substrate and terminating within the fourth doped region; and
a fifth doped region of the first conductive type disposed within the fourth doped region and adjoining the second trench electrode, wherein:
the fifth doped region and the fourth doped region define a fourth diode; and
the second trench electrode is electrically coupled to the first control electrode.
17. A semiconductor device structure comprising:
a semiconductor substrate having a first major surface and an opposing second major surface;
a heterostructure adjacent the first major surface, the heterostructure comprising:
a channel layer; and
a barrier layer over the channel layer;
a first electrode disposed proximate to a first portion of the channel layer;
a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;
a third electrode disposed on the second major surface of the semiconductor substrate;
a first control electrode disposed between the first electrode and the second electrode and configured to control a first current path between the first electrode and the second electrode;
a fourth electrode disposed at least in part proximate to the first major surface, wherein the fourth electrode is electrically coupled to the first electrode; and
a clamping device disposed in the semiconductor substrate and electrically coupled to the fourth electrode, wherein the clamping device comprises a plurality of n-type regions and a plurality of p-type regions disposed in the semiconductor substrate in a back-to-back p-n diode configuration.
18. The semiconductor device structure of claim 17 , wherein:
the second electrode is electrically decoupled from the semiconductor substrate; and
the clamping device is further electrically coupled to the third electrode.
19. The semiconductor device structure of claim 18 , wherein:
the first control electrode is electrically decoupled from the semiconductor substrate;
the semiconductor device structure is further provided in combination with a semiconductor MOSFET device having a third current carrying electrode electrically coupled to the second current carrying electrode, a fourth current carrying electrode electrically coupled to the first control electrode, and a second control electrode; and
the combination comprises a cascode switch structure.
20. The semiconductor device structure of claim 17 , wherein the back-to-back p-n diode configuration is disposed adjoining a dielectric layer within the semiconductor substrate.