IP Library Granted Patent US 10,811,404
Granted Patent B2
US 10,811,404 · App. 16/218,492 · Granted Oct 20, 2020

Package structure and method of manufacturing the same

Inventors: Shih-Ya Huang (Hsinchu, TW); Chung-Hao Tsai (Changhua County, TW); Chen-Hua Yu (Hsinchu, TW); Chuei-Tang Wang (Taichung, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/01H01L21/565H01L21/76816H01L23/3121H01L23/49827H01L24/09H01L2224/02372
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Quick Facts
Patent No.
US 10,811,404
App. No.
16/218,492
Granted
Oct 20, 2020
Kind
B2
Abstract

Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.

Claims (44)

1. A package structure, comprising:

a die having a front side and a backside opposite to each other;

a package disposed on the backside of the die; and

a passive device disposed between the backside of the die and the package.

2. The package structure of claim 1 , further comprising:

a plurality of through insulator vias (TIVs) laterally surrounding the die; and

an encapsulant laterally encapsulating the plurality of TIVs and the die.

3. The package structure of claim 1 , further comprising:

a first redistribution layer (RDL) structure disposed on the front side of the die; and

a second RDL structure disposed between the passive device and the backside of the die.

4. The package structure of claim 1 , wherein an orthographic projection of the passive device projected on a plane extending from the backside of the die partially overlaps with a region of the die.

5. The package structure of claim 1 , wherein an orthographic projection of the passive device projected on a plane extending from the backside of the die is positioned out of a region of the die.

6. The package structure of claim 3 , wherein the passive device has a substrate and a plurality of through semiconductor vias (TSVs) penetrating through the substrate.

7. The package structure of claim 6 , further comprising:

a plurality of first conductive connectors disposed respectively on the first RDL structure;

a plurality of second conductive connectors disposed respectively on the passive device;

a plurality of third conductive connectors disposed respectively laterally aside the passive device and in physical contact with the second RDL structure, wherein a horizontal cross-sectional area of one of the plurality of third conductive connectors is different from a horizontal cross-sectional area of one of the plurality of second conductive connectors at the same level; and

an underfill layer laterally encapsulating the plurality of second conductive connectors, the plurality of third conductive connectors, and the passive device.

8. The package structure of claim 2 , further comprising a second RDL structure disposed between the passive device and the package, wherein the passive device and the die are adhered together in a back-to-back configuration.

9. The package structure of claim 1 , wherein the passive device is in contact with and electrically to the plurality of TIVs.

10. A package structure, comprising:

a die having a front side and a backside opposite to each other;

a passive device disposed aside the die;

a plurality of through insulator vias (TIVs) laterally surrounding the die;

an encapsulant laterally encapsulating the plurality of TIVs, the passive device, and the die;

a front side redistribution layer (RDL) structure disposed on the front side of the die and extending to cover the encapsulant; and

a backside RDL structure disposed on the backside of the die and extending to cover the encapsulant.

11. The package structure of claim 10 , further comprising a package disposed on the backside RDL structure and electrically connected to the passive device.

12. The package structure of claim 11 , wherein the passive device is disposed between and electrically connected to one of the plurality of TIVs and the backside RDL structure.

13. The package structure of claim 10 , further comprising a package disposed on the front side RDL structure and electrically connected to the passive device.

14. The package structure of claim 13 , wherein the passive device laterally disposed between one of the plurality of TIVs and the die.

15. The package structure of claim 10 , further comprising a plurality of conductive connectors disposed on the backside RDL structure and in physical contact with the backside RDL structure.

16. The package structure of claim 14 , wherein the passive device has a substrate and a plurality of through semiconductor vias (TSVs) penetrating through the substrate.

17. A method of manufacturing a package structure, comprising:

forming a backside RDL structure on a backside of a die;

forming a plurality of through insulator vias (TIVs) aside the die to electrically connect to the backside RDL structure;

forming an encapsulant laterally encapsulating the die and the plurality of TIVs;

forming a front side RDL structure on a front side of the die and the encapsulant;

mounting a package on the backside RDL structure; and

mounting a passive device between the backside RDL structure and the package.

18. The method of claim 17 , wherein the passive device forms a plurality of through semiconductor vias (TSVs) therein, the plurality of TSVs are electrically connected to the backside RDL structure.

19. The method of claim 17 , wherein the forming the backside RDL structure on the backside of the die is prior to the forming the front side RDL structure on the front side of the die and the encapsulant.

20. The method of claim 17 , further comprising forming an underfill layer laterally encapsulating the passive device; and

forming a plurality of conductive connectors between the backside RDL structure and the package, wherein the plurality of conductive connectors are in physical contact with the backside RDL structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2018
From: HUANG, SHIH-YA; TSAI, CHUNG-HAO; YU, CHEN-HUA; WANG, CHUEI-TANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 047760/0467 →
Continuity (2)
Provisional Application 62678274 · May 31, 2018
Related Publication 20190371781A1 · Dec 5, 2019
Cited By (1)
US 12,557,704