Photodiode gate dielectric protection layer

1. A method of forming an integrated chip, comprising:

forming a gate dielectric layer over a substrate having a first photodetector region;

forming a gate material over the gate dielectric layer;

forming a dielectric protection layer over the gate dielectric layer; and

forming a first sidewall spacer along a first side of the gate material, wherein the dielectric protection layer extends from a first location directly over the first photodetector region to a top surface that is vertically below a top of the gate material and laterally between the first sidewall spacer and the gate material.

2. The method of claim 1 , wherein the gate dielectric layer extends past the first side of the gate material.

3. The method of claim 1 , wherein the dielectric protection layer is deposited over the gate material and subsequently etched back to below the top of the gate material.

4. The method of claim 1 , further comprising:

forming a masking layer over the substrate, wherein the dielectric protection layer has sidewalls that protrude outward from a top of the masking layer;

etching the dielectric protection layer according to the masking layer; and

removing the masking layer.

5. The method of claim 4 , wherein the masking layer has an upper surface arranged along a horizontal plane that intersects sidewalls of the gate material.

6. The method of claim 4 , further comprising:

forming a hard mask onto a gate material layer over the substrate;

selectively patterning the gate material layer according to the hard mask to define the gate material prior to forming the masking layer; and

removing the hard mask after removing the masking layer.

7. The method of claim 4 , further comprising:

forming a second photodetector region over the first photodetector region after forming the dielectric protection layer, wherein the first photodetector region has a different doping type than the second photodetector region.

8. The method of claim 1 , further comprising:

forming a second masking layer over the first photodetector region;

implanting the substrate to form a floating diffusion region on a second side of the gate material opposing the first side of the gate material; and

removing the second masking layer, wherein removing the second masking layer reduces a thickness of the dielectric protection layer outside of the first sidewall spacer.

9. The method of claim 1 , further comprising:

forming an etch stop layer over the substrate, wherein the etch stop layer contacts a sidewall and an upper surface of the dielectric protection layer.

10. The method of claim 1 , wherein the dielectric protection layer is formed by atomic layer deposition.

11. A method of forming an integrated chip, comprising:

forming a gate dielectric layer over a substrate;

forming a gate material over the gate dielectric layer;

depositing a dielectric protection layer over the gate dielectric layer;

forming sidewalls spacers along sides of the gate material and over a part of the dielectric protection layer; and

reducing a thickness of the dielectric protection layer outside of the sidewall spacers to a non-zero thickness.

12. The method of claim 11 , wherein the dielectric protection layer is formed by atomic layer deposition to an initial thickness in a range of between approximately 30 angstroms and approximately 50 angstroms.

13. The method of claim 11 , wherein the gate dielectric layer is formed to a thickness that is less than approximately 50 angstroms.

14. The method of claim 11 , wherein the dielectric protection layer comprises a first sidewall that protrudes outward from a first upper surface of the dielectric protection layer and a second sidewall that protrudes outward from a second upper surface of the dielectric protection layer.

15. The method of claim 11 , wherein the sidewall spacers cover a topmost surface of the dielectric protection layer.

16. A method of forming an integrated chip, comprising:

forming a gate dielectric layer over a substrate;

forming a conductive gate electrode over the gate dielectric layer;

depositing a dielectric protection layer over the conductive gate electrode;

etching the dielectric protection layer according to a masking layer that has an upper surface below a top of the conductive gate electrode;

removing the masking layer; and

forming a sidewall spacer along a first side of the conductive gate electrode after removing the masking layer.

17. The method of claim 16 , wherein etching the dielectric protection layer removes the dielectric protection layer from above the upper surface of the masking layer.

18. The method of claim 16 ,

wherein the gate dielectric layer has a substantially constant thickness between outermost sidewalls of the gate dielectric layer; and

wherein the dielectric protection layer has a first region having a first thickness and a second region having a second thickness that is less than the first thickness, the first region laterally between the conductive gate electrode and the second region.

19. The method of claim 16 , further comprising:

forming an isolation structure within the substrate, wherein an outermost sidewall of the gate dielectric layer is laterally between the conductive gate electrode and an outermost edge of the isolation structure; and

wherein the dielectric protection layer extends over the isolation structure.

20. The method of claim 16 , further comprising:

etching the dielectric protection layer in areas not covered by the sidewall spacer.