Semiconductor leadframes and packages with solder dams and related methods
A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island. At least one tie bar has a protrusion extending from the upper surface of the leadframe and configured to substantially prevent a flow of a solder between the first and second islands. A first die couples with the leadframe at the first island and a second die couples with the leadframe at the second island. At least one of the tie bars has a recess at a lower surface of the leadframe. The leadframe includes a slit between the first and second island.
1. A leadframe for a semiconductor package, comprising:
a first island comprising a first surface, wherein the first surface of the first island is configured to couple to a die;
a second island; and
one or more tie bars comprising a protrusion extending outward from the first surface of the leadframe above a surface of the first island wherein the first island and the second island are coupled together only through the one or more tie bars;
wherein a second surface of the first island opposing the first surface is configured to couple with a mounting board.
2. The leadframe of claim 1 , wherein the one or more tie bars comprises two tie bars.
3. The leadframe of claim 1 , wherein at least one of the one or more tie bars comprises a recess at a lower surface of the leadframe.
4. The leadframe of claim 1 , wherein the leadframe comprises a slit between the island and the second island.
5. The leadframe of claim 1 , wherein one or more electrical contacts extend from the island and one or more electrical contacts extend from the second island.
6. A semiconductor package, comprising:
a leadframe comprising:
a bonding region comprising at least one die, the bonding region comprising a slit that divides the bonding region; and
a protrusion of at least one of one or more tie bars located adjacent to the slit in the bonding region; and
a mold compound encapsulating the bonding region and the at least one die, and
a plurality of electrical contacts each comprising an exposed surface exposed through the mold compound.
7. The semiconductor package of claim 6 , wherein at least one electrical connector electrically couples the at least one die with at least one of the electrical contacts.
8. The semiconductor package of claim 6 , wherein the one or more tie bars comprises a recess at a lower surface of the leadframe.
9. The semiconductor package of claim 6 , wherein the leadframe further comprises only two tie bars, the two tie bars located on opposing ends of the slit.
10. The semiconductor package of claim 6 , further comprising an upper surface of a first island, the upper surface comprising a largest planar surface of the leadframe.
11. The semiconductor package of claim 10 , further comprising an upper surface of a second island, the upper surface comprising a second largest planar surface of the leadframe.
12. The semiconductor package of claim 6 , wherein the mold compound encapsulates a majority of the bonding region.
13. A semiconductor package, comprising:
a leadframe comprising:
a bonding region comprising at least one die, the at least one die coupled with the leadframe and comprising one of a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or a control integrated circuit configured to control the transistor; and
a first tie bar at a first end of a slit in the bonding region and a second tie bar at a second end of the slit, one of the first tie bar, the second tie bar, or both the first tie bar and the second tie bar comprising a protrusion extending from the surface of the bonding region; and
a mold compound encapsulating the at least one die and the bonding region, and;
a plurality of electrical contacts each comprising an exposed surface exposed through the mold compound.
14. The semiconductor package of claim 13 , wherein at least one electrical connector electrically couples the at least one die with at least one of the electrical contacts.
15. The semiconductor package of claim 13 , wherein the protrusion is configured to substantially prevent a flow of a solder when the at least one die is bonded to the bonding region.
16. The semiconductor package of claim 13 , wherein at least one of the first tie bar or the second tie bar comprises a recess at a lower surface of the first tie bar or the second tie bar.