IP Library › Granted Patent US 10,707,200
Granted Patent B2
US 10,707,200 · App. 16/219,886 · Granted Jul 7, 2020

Semiconductor device

Inventors: Kenji Sasaki (Nagaokakyo, JP); Takayuki Tsutsui (Nagaokakyo, JP); Isao Obu (Nagaokakyo, JP); Yasuhisa Yamamoto (Nagaokakyo, JP)
Assignee: Murata Manufacturing Co., Ltd.
H01L27/0255H01L24/05H01L24/06H01L24/17H01L24/49H01L29/0692H01L29/0821H01L29/1004H01L29/41708H01L29/42304H01L29/7371H01L29/8613H03F1/52H03F3/195H03F3/213H01L24/13H01L24/48H01L2224/02166H01L2224/0401H01L2224/04042H01L2224/13082H01L2224/13101H01L2224/13144H01L2224/48463H01L2924/00014H03F2200/444
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,707,200
App. No.
16/219,886
Granted
Jul 7, 2020
Kind
B2
Abstract

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

Claims (42)

1. A semiconductor device comprising

an amplifier circuit including a semiconductor element formed on a substrate;

a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and

a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein

the pad conductive layer and the protection circuit at least partially overlap each other in plan view,

the plurality of protection diodes constitute a diode array folded back halfway in plan view, and part of the protection circuit is arranged outside the pad conductive layer, and

the plurality of protection diodes include pn junctions.

2. The semiconductor device according to claim 1 , wherein:

the semiconductor element included in the amplifier circuit is a heterojunction bipolar transistor, and

the pn junctions in the plurality of protection diodes are formed of semiconductor layers included in the heterojunction bipolar transistor.

3. The semiconductor device according to claim 2 , wherein:

the substrate, the heterojunction bipolar transistor, and the protection diodes are formed of a compound semiconductor.

4. The semiconductor device according to claim 1 , wherein:

at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

5. The semiconductor device according to claim 2 , wherein:

at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

6. The semiconductor device according to claim 3 , wherein:

at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

7. The semiconductor device according to claim 1 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area, and the opening and the protection circuit at least partially overlapping each other in plan view; and

a bump formed on the pad conductive layer on a bottom surface of the opening.

8. The semiconductor device according to claim 2 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area, and the opening and the protection circuit at least partially overlapping each other in plan view; and

a bump formed on the pad conductive layer on a bottom surface of the opening.

9. The semiconductor device according to claim 3 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area, and the opening and the protection circuit at least partially overlapping each other in plan view; and

a bump formed on the pad conductive layer on a bottom surface of the opening.

10. The semiconductor device according to claim 4 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area, and the opening and the protection circuit at least partially overlapping each other in plan view; and

a bump formed on the pad conductive layer on a bottom surface of the opening.

11. The semiconductor device according to claim 5 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area, and the opening and the protection circuit at least partially overlapping each other in plan view; and

a bump formed on the pad conductive layer on a bottom surface of the opening.

12. The semiconductor device according to claim 6 , further comprising:

an insulating protective film covering the pad conductive layer, the insulating protective film including an opening that exposes a partial area of a surface of the pad conductive layer, the insulating protective film covering another area, and the opening and the protection circuit at least partially overlapping each other in plan view; and

a bump formed on the pad conductive layer on a bottom surface of the opening.

13. The semiconductor device according to claim 7 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

14. The semiconductor device according to claim 8 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

15. The semiconductor device according to claim 9 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

16. The semiconductor device according to claim 10 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

17. The semiconductor device according to claim 11 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

18. The semiconductor device according to claim 12 , wherein a planar shape of the bump is substantially rectangular with rounded corners.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2018
From: SASAKI, KENJI; TSUTSUI, TAKAYUKI; OBU, ISAO; YAMAMOTO, YASUHISA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 047773/0138 →
Priority Claims (2)
JP 2017-035871 · Feb 28, 2017 · national
JP 2017-142136 · Jul 21, 2017 · national
Continuity (2)
Continuation 15902815 · Feb 22, 2018
Related Publication 20190115338A1 · Apr 18, 2019