Manufacturing method of semiconductor device and semiconductor device
Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
1. A semiconductor device including a vertical MOSFET having a planar gate, the semiconductor device comprising:
a gallium nitride monocrystalline substrate;
a gallium nitride layer on the gallium nitride monocrystalline substrate; and
an impurity-implanted region formed in the gallium nitride layer, the impurity-implanted region containing impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, the impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein
at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET, and
the gallium nitride layer on the gallium nitride monocrystalline substrate has a threading dislocation density of less than 1E+7 cm −2 .
2. A semiconductor device including a vertical MOSFET having a planar gate, the semiconductor device comprising:
a gallium nitride monocrystalline substrate;
an n-type gallium nitride layer on the gallium nitride monocrystalline substrate; and
a p-type impurity-implanted region formed in the n-type gallium nitride layer, the p-type impurity-implanted region containing impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, the p-type impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein
at least part of the p-type impurity-implanted region serves as a channel forming region of the vertical MOSFET, and
the gallium nitride layer on the gallium nitride monocrystalline substrate has a threading dislocation density of less than 1E+7 cm −2 .
3. The semiconductor device including a vertical MOSFET having a planar gate according to claim 1 , wherein:
the impurities include Mg at an amount of 1E+19 cm −3 .
4. The semiconductor device including a vertical MOSFET having a planar gate according to claim 2 , wherein:
the impurities include Mg at an amount of 1E+19 cm −3 .