Memory system design using buffer(S) on a mother board
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.
1. A system comprising:
a processor coupled to a plurality of communication channels to communicate commands;
a first shared primary data buffer;
a second shared primary data buffer;
a first communication channel of the plurality of communication channels electrically coupling the first shared primary data buffer to a first plurality of dual in-line memory modules (DIMMs), wherein each DIMM of the first plurality of DIMMs is coupled in parallel to the first shared primary data buffer via the first communication channel;
a second communication channel of the plurality of communication channels electrically coupling the second shared primary data buffer to a second plurality of DIMMs, wherein each DIMM of the second plurality of DIMMs is coupled in parallel to the second shared primary data buffer via the second communication channel; and
a third communication channel of the plurality of communication channels electrically coupling the first shared primary data buffer to the second shared primary data buffer, and coupling the first shared primary data buffer and the second shared primary data buffer to the processor.
2. The system of claim 1 , wherein the processor comprises a programmable controller, and wherein the programmable controller is configured to respond to commands to access data stored in one or more of a plurality of memory devices distributed throughout the first plurality of DIMMs and the second plurality of DIMMs and to perform data operations on the data accessed from the one or more of the plurality of memory devices.
3. The system of claim 2 , wherein the programmable controller comprises a field programmable gate array (FPGA).
4. The system of claim 2 , wherein the one or more of the plurality of memory devices comprise memory devices packaged in a DIMM comprising at least one of a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), or an unregistered DIMM (UDIMM).
5. The system of claim 1 , wherein the first plurality of DIMMs and the second plurality of DIMMs comply with a double data-rate (DDR) standard.
6. The system of claim 1 , further comprising:
a plurality of I2C buses, each I2C bus coupling the processor to a corresponding DIMM in the first plurality of DIMMs or the second plurality of DIMMs and configured for communicating an alert.
7. The system of claim 1 , further comprising:
a plurality of I2C buses, each I2C bus coupling the processor to a corresponding DIMM in the first plurality of DIMMs or the second plurality of DIMMs and configured for performing calibration.
8. The system of claim 1 , wherein the third communication channel comprises a BCOM bus.
9. A system comprising:
a plurality of memory devices;
a memory controller configured to respond to commands from a command interface to access data stored in one or more of the plurality of memory devices and to perform data operations on the data accessed from the plurality of memory devices;
a first communication channel electrically coupling a first shared primary data buffer to a first plurality of dual in-line memory modules (DIMMs), wherein each DIMM of the first plurality of DIMMs is coupled in parallel to the first shared primary data buffer via the first communication channel;
a second communication channel electrically coupling a second shared primary data buffer to a second plurality of DIMMs, wherein each DIMM of the second plurality of DIMMs is coupled in parallel to the second shared primary data buffer via the second communication channel; and
a third communication channel electrically coupling the first shared primary data buffer to the second shared primary data buffer, and coupling the first shared primary data buffer and the second shared primary data buffer to the memory controller.
10. The system of claim 9 , wherein the memory controller is programmable.
11. The system of claim 9 , wherein the memory controller comprises a field programmable gate array (FPGA).
12. The system of claim 9 , wherein the plurality of memory devices comprise memory devices packaged in a registered DIMM (RDIMM).
13. The system of claim 9 , wherein the plurality of memory devices comprise memory devices packaged in a load reduced DIMM (LRDIMM).
14. The system of claim 9 , wherein the plurality of memory devices comprise memory devices packaged in an unregistered DIMM (UDIMM).
15. The system of claim 9 , wherein the first shared primary data buffer and the second shared primary data buffer are configured to sample and retransmit data.
16. A memory unit comprising:
a processor coupled to a plurality of communication channels to communicate commands;
a first communication channel of the plurality of communication channels electrically coupling a first shared primary data buffer to a first plurality of dual in-line memory modules (DIMMs), wherein each DIMM of the first plurality of DIMMs is coupled in parallel to the first shared primary data buffer via the first communication channel;
a second communication channel of the plurality of communication channels electrically coupling a second shared primary data buffer to a second plurality of DIMMs, wherein each DIMM of the second plurality of DIMMs is coupled in parallel to the second shared primary data buffer via the second communication channel; and
a third communication channel of the plurality of communication channels electrically coupling the first shared primary data buffer to the second shared primary data buffer, and coupling the first shared primary data buffer and the second shared primary data buffer to the processor.
17. The memory unit of claim 16 , wherein the processor comprises a programmable controller, and wherein the programmable controller is configured to respond to the commands to access data stored in one or more of a plurality of memory devices distributed throughout the first plurality of DIMMs and the second plurality of DIMMs and to perform data operations on the data accessed from the one or more of the plurality of memory devices.
18. The memory unit of claim 17 , wherein the programmable controller comprises a field programmable gate array (FPGA).
19. The memory unit of claim 17 , wherein the one or more of the plurality of memory devices comprise memory devices packaged in a DIMM comprising at least one of a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), or an unregistered DIMM (UDIMM).
20. The memory unit of claim 17 , wherein the first plurality of DIMMs and the second plurality of DIMMs comply with a double data-rate (DDR) standard.