Semiconductor device
View Patent ↗One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the fourth transistor, and a first gate line,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, and a gate of the sixth transistor,
wherein a gate of the third transistor is directly connected to the other of the source and the drain of the third transistor and a second gate line,
wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,
wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the seventh transistor, and
wherein a signal whose potential is changed is input to the other of the source and the drain of the second transistor.
2. The semiconductor device according to claim 1 , wherein the first transistor comprises a semiconductor layer comprising amorphous silicon, the semiconductor layer comprising a channel region.
3. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the fourth transistor, a first electrode of the capacitor, and a first gate line,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, a gate of the sixth transistor, and a second electrode of the capacitor,
wherein a gate of the third transistor is directly connected to the other of the source and the drain of the third transistor and a second gate line,
wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,
wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the seventh transistor,
wherein a signal whose potential is changed is input to the other of the source and the drain of the second transistor,
wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor.
4. The semiconductor device according to claim 3 , wherein the first transistor comprises a semiconductor layer comprising amorphous silicon, the semiconductor layer comprising a channel region.
5. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the fourth transistor, a first electrode of the capacitor, and a first gate line,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, a gate of the sixth transistor, and a second electrode of the capacitor,
wherein a gate of the third transistor is directly connected to the other of the source and the drain of the third transistor and a second gate line,
wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,
wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the seventh transistor,
wherein a signal whose potential is changed is input to the other of the source and the drain of the second transistor,
wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor,
wherein the other of the source and the drain of the first transistor is directly connected to a signal line, and
wherein each of the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the sixth transistor is directly connected to a power supply line.
6. The semiconductor device according to claim 5 , wherein the first transistor comprises a semiconductor layer comprising amorphous silicon, the semiconductor layer comprising a channel region.