IP Library › Granted Patent US 12,294,031
Granted Patent B2
US 12,294,031 · App. 18/422,699 · Granted May 6, 2025

Semiconductor device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869G09G3/20G09G3/3648G11C19/28H01L21/477H01L27/1255H01L27/127G09G2300/04G09G2310/0275
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Quick Facts
Patent No.
US 12,294,031
App. No.
18/422,699
Granted
May 6, 2025
Kind
B2
Abstract

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Claims (56)

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,

wherein the other of the source and the drain of the first transistor is electrically connected to an output signal line,

wherein one of a source and a drain of the second transistor is electrically connected to the output signal line,

wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a second power supply line,

wherein a gate of the third transistor is electrically connected to a first signal line,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first power supply line,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,

wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the one of the source and the drain of the fifth transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor,

wherein a gate of the seventh transistor is electrically connected to the other of the source and the drain of the fifth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first power supply line,

wherein a gate of the eighth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the seventh transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the first power supply line,

wherein a gate of the ninth transistor is electrically connected to a second signal line,

wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to the first power supply line, and

wherein a gate of the tenth transistor is electrically connected to the second signal line.

2. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,

wherein the other of the source and the drain of the first transistor is electrically connected to an output signal line,

wherein one of a source and a drain of the second transistor is electrically connected to the output signal line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a second power supply line,

wherein a gate of the third transistor is electrically connected to a first signal line,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a first power supply line,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,

wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the one of the source and the drain of the fifth transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor,

wherein a gate of the seventh transistor is electrically connected to the other of the source and the drain of the fifth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first power supply line,

wherein a gate of the eighth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the seventh transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the first power supply line,

wherein a gate of the ninth transistor is electrically connected to a second signal line,

wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to the first power supply line,

wherein a gate of the tenth transistor is electrically connected to the second signal line, and

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2024
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 066249/0953 →
Priority Claims (1)
JP 2009-077955 · Mar 27, 2009 · national
Continuity (10)
Continuation 17946116 · Sep 16, 2022
Continuation 17408572 · Aug 23, 2021
Continuation 16925381 · Jul 10, 2020
Continuation 16416394 · May 20, 2019
Continuation 16244193 · Jan 10, 2019
Continuation 16022806 · Jun 29, 2018
Continuation 15168293 · May 31, 2016
Continuation 13975422 · Aug 26, 2013
Continuation 12731722 · Mar 25, 2010
Related Publication 20240413249A1 · Dec 12, 2024
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