IP Library › Granted Patent US 10,714,630
Granted Patent B2
US 10,714,630 · App. 16/416,394 · Granted Jul 14, 2020

Semiconductor device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869G09G3/20G09G3/3648G11C19/28H01L21/477H01L27/127H01L27/1255G09G2300/04G09G2310/0275
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Quick Facts
Patent No.
US 10,714,630
App. No.
16/416,394
Granted
Jul 14, 2020
Kind
B2
Abstract

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Claims (107)

1. A semiconductor device comprising:

a pixel portion, a first circuit, a second circuit, and a third circuit;

wherein the first circuit comprises first to ninth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,

wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the second transistor,

wherein a gate of the second transistor is electrically connected to the other of the source and the drain of the second transistor,

wherein the gate of the second transistor is electrically connected to a third wiring,

wherein a gate of the third transistor is electrically connected to a fourth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the fifth wiring,

wherein a gate of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the fourth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the fifth wiring,

wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the fifth wiring,

wherein a gate of the ninth transistor is electrically connected to the gate of the first transistor,

wherein a first clock signal is input to the first wiring,

wherein a signal is output to the second wiring, and the second wiring is electrically connected to the second circuit and a gate of a transistor of the pixel portion,

wherein a signal output from the third circuit is input to the third wiring,

wherein a second clock signal is input to the fourth wiring,

wherein a power supply potential is input to the fifth wiring, and

wherein a channel width of each of the second to the ninth transistors is smaller than a channel width of the first transistor.

2. The semiconductor device according to claim 1 ,

wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the first transistor is directly connected to the second wiring,

wherein the one of the source and the drain of the second transistor is directly connected to the one of the source and the drain of the third transistor,

wherein the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the third transistor,

wherein the gate of the first transistor is directly connected to the one of the source and the drain of the second transistor,

wherein the gate of the second transistor is directly connected to the other of the source and the drain of the second transistor,

wherein the gate of the second transistor is directly connected to the third wiring,

wherein the gate of the third transistor is directly connected to the fourth wiring,

wherein the one of the source and the drain of the fourth transistor is directly connected to the other of the source and the drain of the first transistor,

wherein the other of the source and the drain of the fourth transistor is directly connected to the fifth wiring,

wherein the one of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to the fifth wiring,

wherein the gate of the fifth transistor is directly connected to the gate of the fourth transistor,

wherein the one of the source and the drain of the sixth transistor is directly connected to the gate of the fourth transistor,

wherein the one of the source and the drain of the seventh transistor is directly connected to the gate of the fourth transistor,

wherein the other of the source and the drain of the seventh transistor is directly connected to the fifth wiring,

wherein the gate of the seventh transistor is directly connected to the gate of the first transistor,

wherein the one of the source and the drain of the eighth transistor is directly connected to the gate of the sixth transistor,

wherein the other of the source and the drain of the eighth transistor is directly connected to the other of the source and the drain of the sixth transistor,

wherein the gate of the eighth transistor is directly connected to the other of the source and the drain of the sixth transistor,

wherein the one of the source and the drain of the ninth transistor is directly connected to the gate of the sixth transistor,

wherein the other of the source and the drain of the ninth transistor is directly connected to the fifth wiring,

wherein the gate of the ninth transistor is directly connected to the gate of the first transistor, and

wherein the second wiring is directly connected to the second circuit and the gate of the transistor of the pixel portion.

3. A semiconductor device comprising:

first to ninth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, and a first gate signal line,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, a gate of the seventh transistor, and a gate of the ninth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the second transistor, the other of the source and the drain of the third transistor, and a second gate signal line,

wherein a gate of the third transistor is electrically connected to a second wiring,

wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor, and a gate of the eighth transistor,

wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and one of a source and a drain of the ninth transistor,

wherein a first clock signal is input to the first wiring,

wherein a second clock signal is input to the second wiring,

wherein a power supply line is electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the ninth transistor, and

wherein a channel width of each of the second to the ninth transistors is smaller than a channel width of the first transistor.

4. The semiconductor device according to claim 3 ,

wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the first transistor is directly connected to the one of the source and the drain of the fourth transistor, and the first gate signal line,

wherein the gate of the first transistor is directly connected to the one of the source and the drain of the second transistor, the one of the source and the drain of the third transistor, the gate of the seventh transistor, and the gate of the ninth transistor,

wherein the other of the source and the drain of the second transistor is directly connected to the gate of the second transistor, the other of the source and the drain of the third transistor, and the second gate signal line,

wherein the gate of the third transistor is directly connected to the second wiring,

wherein the gate of the fourth transistor is directly connected to the gate of the fifth transistor, the one of the source and the drain of the sixth transistor, and the one of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the sixth transistor is directly connected to the one of the source and the drain of the eighth transistor, and the gate of the eighth transistor,

wherein the gate of the sixth transistor is directly connected to the other of the source and the drain of the eighth transistor, and the one of the source and the drain of the ninth transistor, and

wherein the power supply line is directly connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the ninth transistor.

5. A semiconductor device comprising:

a plurality of circuit each of which outputs a signal to a pixel portion; and

a circuit which outputs no signal to the pixel portion,

wherein the circuit comprises first to ninth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, a gate of the seventh transistor, and a gate of the ninth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the second transistor, the other of the source and the drain of the third transistor, and a gate signal line,

wherein a gate of the third transistor is electrically connected to a second wiring,

wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor, and a gate of the eighth transistor,

wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and one of a source and a drain of the ninth transistor,

wherein a first clock signal is input to the first wiring,

wherein a second clock signal is input to the second wiring,

wherein a power supply line is electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the ninth transistor, and

wherein a channel width of each of the second to the ninth transistors is smaller than a channel width of the first transistor.

6. The semiconductor device according to claim 5 ,

wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the first transistor is directly connected to the one of the source and the drain of the fourth transistor,

wherein the gate of the first transistor is directly connected to the one of the source and the drain of the second transistor, the one of the source and the drain of the third transistor, the gate of the seventh transistor, and the gate of the ninth transistor,

wherein the other of the source and the drain of the second transistor is directly connected to the gate of the second transistor, the other of the source and the drain of the third transistor, and the gate signal line,

wherein the gate of the third transistor is directly connected to the second wiring,

wherein the gate of the fourth transistor is directly connected to the gate of the fifth transistor, the one of the source and the drain of the sixth transistor, and the one of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the sixth transistor is directly connected to the one of the source and the drain of the eighth transistor, and the gate of the eighth transistor,

wherein the gate of the sixth transistor is directly connected to the other of the source and the drain of the eighth transistor, and the one of the source and the drain of the ninth transistor, and

wherein the power supply line is directly connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the ninth transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2019
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 049327/0452 →
Priority Claims (1)
JP 2009-077955 · Mar 27, 2009 · national
Continuity (6)
Continuation 16244193 · Jan 10, 2019
Continuation 16022806 · Jun 29, 2018
Continuation 15168293 · May 31, 2016
Continuation 13975422 · Aug 26, 2013
Continuation 12731722 · Mar 25, 2010
Related Publication 20190312146A1 · Oct 10, 2019
Cited By (1)
US 12,294,031