Semiconductor device
View Patent ↗One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a wiring to which a clock signal is input,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, and a first gate signal line,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, a gate of the seventh transistor, and a gate of the ninth transistor,
wherein a gate of the second transistor is electrically connected to a second gate signal line,
wherein a gate of the third transistor is electrically connected to a signal line,
wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor, and a gate of the eighth transistor,
wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and one of a source and a drain of the ninth transistor,
wherein a power supply line is electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the ninth transistor.
2. The semiconductor device according to claim 1 , wherein a channel width of each of the second to the ninth transistors is smaller than a channel width of the first transistor.
3. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, and a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, a gate of the seventh transistor, and a gate of the ninth transistor,
wherein a gate of the second transistor is electrically connected to a third wiring,
wherein a gate of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor, and a gate of the eighth transistor,
wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and one of a source and a drain of the ninth transistor,
wherein a fifth wiring is electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the seventh transistor, and the other of the source and the drain of the ninth transistor.
4. The semiconductor device according to claim 3 , wherein a channel width of each of the second to the ninth transistors is smaller than a channel width of the first transistor.