Semiconductor device

Inventor: Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L29/7869 G09G3/20 G09G3/3648 G11C19/28 H01L21/477 H01L27/127 H01L27/1255 G09G2300/04 G09G2310/0275

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Quick Facts

Patent No.: US 11,916,150
App. No.: 17/946,116
Granted: Feb 27, 2024
Kind: B2

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Abstract

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Claims (49)

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring for inputting a clock signal,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring for outputting an output signal,

wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a first signal line,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a second signal line,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the first power supply line,

wherein a gate of the fifth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to a second power supply line,

wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor and one of a source and a drain of the ninth transistor,

wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to the first power supply line,

wherein a gate of the tenth transistor is electrically connected to the gate of the first transistor, and

wherein a potential of the first power supply line is lower than a potential of the second power supply line.

2. A semiconductor device comprising:

a first scan line driver circuit configured to scan wirings in odd-numbered rows;

a second scan line driver circuit configured to scan wirings in even-numbered rows; and

a pixel portion provided between the first scan line driver circuit and the second scan line driver circuit, the pixel portion comprising a plurality of pixels,

wherein each of the plurality of pixels comprises a liquid crystal element,

wherein at least one of the first scan line driver circuit and the second scan line driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring for inputting a clock signal,

wherein the other of the source and the drain of the first transistor is electrically connected to the pixel through a second wiring for outputting an output signal,