Stacked DRAM device and method of manufacture
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
1. A memory device comprising:
a first integrated circuit (IC) memory chip including
first memory core circuitry, and
first input/output (I/O) circuitry electrically coupled to the first memory core circuitry;
a second IC memory chip vertically stacked with the first IC memory chip, the second IC memory chip including
second memory core circuitry, and
second I/O circuitry decoupled from the second memory core circuitry; and
wherein data transfers involving the second memory core circuitry and an off-chip memory controller bypass the second I/O circuitry and are routed to the first I/O circuitry.
2. The memory device according to claim 1 , wherein:
the first input/output (I/O) circuitry electrically couples to the first memory core circuitry via a first conductive path; and
the second memory IC chip is configured without a conductive path corresponding to the first conductive path.
3. The memory device according to claim 2 , wherein a first portion of the first conductive path is formed in a metal layer.
4. Previously Presented) The memory device according to claim 3 , wherein the metal layer comprises:
a redistribution layer formed during a packaging process.
5. The memory device according to claim 3 , wherein a second portion of the conductive path is formed in at least one through-silicon-via (TSV).
6. The memory device according to claim 5 , wherein:
the first conductive path electrically couples the first memory core circuitry to the first I/O circuitry via the metal layer and the at least one TSV.
7. The memory device according to claim 1 , wherein:
the first and second memory IC chips comprise dynamic random access memory (DRAM) integrated circuit (IC) chips.
8. A memory module, comprising:
a substrate;
multiple memory devices mounted to the substrate, each memory device comprising
multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each of the multiple DRAM IC chips including
memory core circuitry, and
input/output (I/O) circuitry; and
wherein data transfers involving a first one of the multiple DRAM IC chips and an off-chip memory controller are routed to the I/O circuitry of the first one of the multiple DRAM IC chips via a conductive path; and
wherein data transfers involving a second one of the multiple DRAM IC chips and an off-chip memory controller bypass the I/O circuitry of the second one of the multiple DRAM IC chips and are routed to the I/O circuitry of the first one of the multiple DRAM IC chips.
9. The memory module according to claim 8 , wherein:
a first portion of the conductive path is formed in a metal layer.
10. The memory module according to claim 9 , wherein the metal layer comprises:
a redistribution layer formed during a packaging process.
11. The memory module according to claim 9 , wherein:
a second portion of the conductive path is formed in at least one through-silicon-via (TSV).
12. The memory module according to claim 11 , wherein:
the conductive path electrically couples memory core circuitry of the first one of the multiple DRAM IC chips to the I/O circuitry of the first one of the multiple DRAM IC chips via the metal layer and the at least one TSV.
13. The memory module according to claim 8 , wherein:
for the first one of the multiple DRAM IC chips, the I/O circuitry electrically couples to the memory core circuitry via the conductive path; and
for the second one of the multiple DRAM IC chips, the second memory IC chip is configured without the conductive path.
14. The memory module according to claim 13 , wherein:
the second one of the multiple DRAM IC chips is configured with the I/O circuitry electrically decoupled from the memory core circuitry.
15. A memory, comprising:
at least one memory module including
a substrate;
multiple memory devices mounted to the substrate, each memory device comprising
multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each of the multiple DRAM IC chips including
memory core circuitry, and
input/output (I/O) circuitry; and
wherein data transfers involving a first one of the multiple DRAM IC chips and an off-chip memory controller are routed to the I/O circuitry of the first one of the multiple DRAM IC chips via a conductive path; and
wherein data transfers involving a second one of the multiple DRAM IC chips and an off-chip memory controller bypass the I/O circuitry of the second one of the multiple DRAM IC chips and are routed to the I/O circuitry of the first one of the multiple DRAM IC chips.
16. The memory according to claim 15 , wherein:
a first portion of the conductive path is formed in a metal layer.
17. The memory according to claim 16 , wherein the metal layer comprises:
a redistribution layer formed during a packaging process.
18. The memory according to claim 16 , wherein:
a second portion of the conductive path is formed in at least one through-silicon-via (TSV).
19. The memory according to claim 18 , wherein:
the conductive path electrically couples the memory core circuitry of the first one of the multiple DRAM IC chips to the I/O circuitry of the first one of the multiple DRAM IC chips via the metal layer and the at least one TSV.
20. The memory according to claim 15 , wherein:
for the first one of the multiple DRAM IC chips, the I/O circuitry electrically couples to the memory core circuitry via the conductive path; and
for the second one of the multiple DRAM IC chips, the second memory IC chip is configured without the conductive path.