Method of forming fine interconnection for a semiconductor device

1. A method of forming fine interconnection for a semiconductor device, comprising:

forming a plurality of spacers on a first and second hard mask layer on a dielectric layer, wherein the first hard mask layer is between the second hard mask layer and the dielectric layer;

forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer;

oxidizing a sidewall of the first hard mask layer that surrounding the via hole;

forming a second via hole in the second hard mask layer;

selectively forming a mask to cover the first hard mask layer that is in the second via hole such that the second hard mask layer, the side wall of the first hard mask layer, and the dielectric layer in the first via hole are spaced apart from the mask;

forming a line trench in a portion of the second hard mask layer exposed by the spacers, and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and

forming a conductive material in the line trench and the first via hole.

2. The method of claim 1 , wherein the forming the via hole further comprising:

forming a planarization layer to cover the spacers and the second hard mask layer;

forming a photoresist layer on the planarization layer; and

forming an opening in the photoresist layer, wherein the opening is above at least two adjacent spacers, and the first via hole is below the opening.

3. The method of claim 2 , further comprising:

removing the planarization layer and the photoresist layer after forming the first via hole.

4. The method of claim 1 , wherein oxidizing the sidewall of the first hard mask layer is performed by oxygen plasma.

5. The method of claim 1 , wherein forming the second via hole further comprising:

forming a planarization layer to cover the spacers, the first via hole, and the second hard mask layer;

forming a photoresist layer on the planarization layer; and

forming an opening in the photoresist layer, wherein the opening is above at least two adjacent spacers, and the second via hole is below the opening.

6. The method of claim 1 , wherein the mask is made of a material comprises metal oxide.

7. The method of claim 1 , further comprising:

forming a planarization layer to fill the first via hole and cover the spacers, the mask, and the second hard mask layer after forming the mask.

8. The method of claim 7 , further comprising:

removing the planarization layer until the mask and the second hard mask layer are exposed, such that a remaining portion of the planarization layer is in the first via hole.

9. The method of claim 8 , wherein forming the line trench such that a top surface of the remaining portion of the planarization layer is lower than the second hard mask layer.

10. The method of claim 1 , further comprising:

removing the first and the second hard mask layer, the mask, and the planarization layer in the first via hole.

11. The method of claim 1 , further comprising:

forming a core layer on the second hard mask layer; and

patterning the core layer.

12. The method of claim 11 , wherein forming the spacers on the first and second hard mask layer further comprising:

forming the spacers on a sidewall of the patterned core layer; and

removing the patterned core layer.