Method of manufacturing a CMOS transistor
A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
1. A semiconductor device, comprising:
a first isolation region formed in a semiconductor substrate;
a gate insulating film formed on the semiconductor substrate;
a first gate electrode pattern formed on the gate insulating film;
a p-type well region formed below the first gate electrode pattern;
an n-type source region and an n-type drain region formed in the p-type well region,
wherein a bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the p-type well region below the n-type source region and the n-type drain region;
a second gate electrode pattern formed adjacent to the first gate electrode pattern;
an n-type well region formed below the second gate electrode pattern, the n-type well region being in direct contact with the p-type well region; and
a p-type source region and a p-type drain region formed in the n-type well region, wherein a bottom surface of the n-type well region below the second gate electrode pattern is shallower than a bottom surface of the n-type well region below the p-type source region and the p-type drain region.
2. The semiconductor device of claim 1 ,
wherein the p-type well region is formed deeper than the first isolation region, and
the bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the p-type well region below the first isolation region.
3. The semiconductor device of claim 1 ,
wherein the n-type well region is formed deeper than the first isolation region, and
the bottom surface of the n-type well region below the second gate electrode pattern is shallower than a bottom surface of the n-type well region below the first isolation region.
4. The semiconductor device of claim 1 , wherein the n-type well region and the p-type well region are in direct contact with each other below the first isolation region.
5. The semiconductor device of claim 1 , wherein a depth of the p-type well region below the first gate electrode pattern is similar to a depth of the n-type well region below the second gate electrode pattern.
6. The semiconductor device of claim 1 , wherein the bottom surface of the p-type well region below the first gate electrode pattern is shallower than the bottom surface of the n-type well region below the p-type source region.
7. The semiconductor device of claim 1 , wherein the bottom surface of the n-type well region below the second gate electrode pattern is shallower than the bottom surface of the p-type well region below the n-type source region.
8. The semiconductor device of claim 1 , wherein the gate insulating film extends under a spacer formed on sidewall of the first gate electrode pattern.
9. A semiconductor device, comprising:
a semiconductor substrate having an isolation region;
a first gate insulating film and a second gate insulating film formed on the semiconductor substrate;
a first gate electrode pattern and a second gate electrode pattern formed on the first gate insulating film and the second gate insulating film, respectively;
a p-type well region and a n-type well region below the first gate electrode pattern and the second gate electrode pattern, respectively;
an n-type source region and an n-type drain region formed in the p-type well region; and
an p-type source region and an p-type drain region formed in the n-type well region,
wherein the p-type well region is in direct contact with the n-type well region below the isolation region,
wherein a bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the p-type well region below the n-type source region, and
wherein a bottom surface of the n-type well region below the second gate electrode pattern is shallower than a bottom surface of the n-type well region below the p-type source region.
10. The semiconductor device of claim 9 , wherein the bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the n-type well region below the p-type source region.
11. The semiconductor device of claim 9 , wherein the bottom surface of the n-type well region below the second gate electrode pattern is shallower than the bottom surface of the p-type well region below the n-type source region.
12. The semiconductor device of claim 9 , wherein a depth of the p-type well region below the first gate electrode pattern is similar to a depth of the n-type well region below the second gate electrode pattern.
13. The semiconductor device of claim 9 ,
wherein the bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the p-type well region below the isolation region, and
wherein the bottom surface of the n-type well region below the second gate electrode pattern is shallower than a bottom surface of the n-type well region below the isolation region.
14. The semiconductor device of claim 9 , wherein the first gate insulating film extends under a first spacer formed on sidewall of the first gate electrode pattern.
15. A semiconductor device, comprising:
a semiconductor substrate having an isolation region;
a first gate insulating film and a second gate insulating film formed on the semiconductor substrate;
a first gate electrode pattern and a second gate electrode pattern formed on the first gate insulating film and the second gate insulating film, respectively;
a p-type well region and a n-type well region below the first gate electrode pattern and the second gate electrode pattern, respectively, the p-type well region being in direct contact with the n-type well region;
an n-type source region and an n-type drain region formed in the p-type well region; and
an p-type source region and an p-type drain region formed in the n-type well region,
wherein a bottom surface of the n-type well region below the second gate electrode pattern is shallower than a bottom surface of the n-type well region below the p-type source region and p-type drain region, and
wherein the bottom surface of the n-type well region below the second gate electrode pattern is shallower than a bottom surface of the n-type well region below the isolation region.
16. The semiconductor device of claim 15 , wherein a bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the p-type well region below the n-type source region and the n-type drain region, and
wherein Previously Presented the bottom surface of the p-type well region below the first gate electrode pattern is shallower than a bottom surface of the p-type well region below the isolation region.
17. The semiconductor device of claim 15 , wherein the p-type well region is in direct contact with the n-type well region below the isolation region.