IP Library Granted Patent US 10,854,720
Granted Patent B2
US 10,854,720 · App. 16/262,352 · Granted Dec 1, 2020

Semiconductor device manufacturing method

Inventor: Wen-Chia Liao (Taoyuan, TW)
Assignee: DELTA ELECTRONICS, INC.
H01L29/402H01L23/3171H01L29/66462H01L29/7786H01L23/291H01L29/1066H01L29/2003H01L29/404H01L2924/0002
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Quick Facts
Patent No.
US 10,854,720
App. No.
16/262,352
Granted
Dec 1, 2020
Kind
B2
Abstract

A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.

Claims (11)

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate;

forming an active layer on the substrate;

forming a p-type doped layer on the active layer, wherein the p-type doped layer has a first thickness;

forming a gate electrode on the p-type doped layer;

forming a passivation layer to cover the gate electrode and the active layer after forming the gate electrode;

forming a source via hole, a drain via hole, and a blind hole in the passivation layer, wherein the p-type doped layer is disposed between the source via hole and the blind hole, the blind hole is disposed between the p-type doped layer and the drain via hole, a portion of the passivation layer under the blind hole has a second thickness smaller than the first thickness; and

respectively forming a source electrode, a conductive plate and a drain electrode in the source via hole, the blind hole, and the drain via hole.

2. The manufacturing method of claim 1 , wherein the p-type doped layer is made of GaN or AlGaN doped with p-type dopants.

3. The manufacturing method of claim 1 , wherein forming the blind hole comprises:

forming a step at a side of the blind hole facing the active layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2022
From: DELTA ELECTRONICS, INC.
To: ANCORA SEMICONDUCTORS INC.
Reel/Frame 061648/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: LIAO, WEN-CHIA
To: DELTA ELECTRONICS, INC.
Reel/Frame 048192/0478 →
Continuity (3)
Division 14724963 · May 29, 2015
Provisional Application 62008600 · Jun 6, 2014
Related Publication 20190172915A1 · Jun 6, 2019
Cited By (1)
US 12,295,165