Using a layer performance metric (LPM) to perform placement, routing, and/or optimization of an integrated circuit (IC) design
Techniques and systems for using a layer performance metric (LPM) during integrated circuit (IC) design are described. Some embodiments can compute an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path. Next, the embodiments can use the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.
1. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for using a layer performance metric (LPM) during integrated circuit (IC) design, the method comprising:
computing an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path; and
using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.
2. The non-transitory computer-readable storage medium of claim 1 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises assigning a set of metal layers to a net in the timing path based on the LPM value, wherein a router uses the set of metal layers while routing the net.
3. The non-transitory computer-readable storage medium of claim 1 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises computing a routing feasibility indicator based on the LPM value, wherein the routing feasibility indicator indicates an amount of routing congestion that is expected to occur while routing the IC design.
4. The non-transitory computer-readable storage medium of claim 1 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises computing a timing feasibility indicator based on the LPM value, wherein the timing feasibility indicator indicates whether or not the timing path is expected to meet a timing constraint for the timing path.
5. The non-transitory computer-readable storage medium of claim 1 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises assigning a priority level to a net in the timing path based on the LPM value, wherein a router prevents detours and prevents demotion to lower performance layers while routing nets in the IC design that have a high priority level.
6. The non-transitory computer-readable storage medium of claim 1 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises selecting a size of a buffer in the timing path based on the LPM value.
7. A method for using a layer performance metric (LPM) during integrated circuit (IC) design, the method comprising:
computing, by using a computer, an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path; and
using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.
8. The method of claim 7 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises assigning a set of metal layers to a net in the timing path based on the LPM value, wherein a router uses the set of metal layers while routing the net.
9. The method of claim 7 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises computing a routing feasibility indicator based on the LPM value, wherein the routing feasibility indicator indicates an amount of routing congestion that is expected to occur while routing the IC design.
10. The method of claim 7 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises computing a timing feasibility indicator based on the LPM value, wherein the timing feasibility indicator indicates whether or not the timing path is expected to meet a timing constraint for the timing path.
11. The method of claim 7 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises assigning a priority level to a net in the timing path based on the LPM value, wherein a router prevents detours and prevents demotion to lower performance layers while routing nets in the IC design that have a high priority level.
12. The method of claim 7 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises selecting a size of a buffer in the timing path based on the LPM value.
13. An apparatus, comprising:
a processor; and
a non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for using a layer performance metric (LPM) during integrated circuit (IC) design, the method comprising:
computing an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path; and
using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.
14. The apparatus of claim 13 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises assigning a set of metal layers to a net in the timing path based on the LPM value, wherein a router uses the set of metal layers while routing the net.
15. The apparatus of claim 13 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises computing a routing feasibility indicator based on the LPM value, wherein the routing feasibility indicator indicates an amount of routing congestion that is expected to occur while routing the IC design.
16. The apparatus of claim 13 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises computing a timing feasibility indicator based on the LPM value, wherein the timing feasibility indicator indicates whether or not the timing path is expected to meet a timing constraint for the timing path.
17. The apparatus of claim 13 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises assigning a priority level to a net in the timing path based on the LPM value, wherein a router prevents detours and prevents demotion to lower performance layers while routing nets in the IC design that have a high priority level.
18. The apparatus of claim 13 , wherein using the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path comprises selecting a size of a buffer in the timing path based on the LPM value.