Speech recognition circuit using parallel processors
A speech recognition circuit comprises an input buffer for receiving processed speech parameters. A lexical memory contains lexical data for word recognition. The lexical data comprises a plurality of lexical tree data structures. Each lexical tree data structure comprises a model of words having common prefix components. An initial component of each lexical tree structure is unique. A plurality of lexical tree processors are connected in parallel to the input buffer for processing the speech parameters in parallel to perform parallel lexical tree processing for word recognition by accessing the lexical data in the lexical memory. A results memory is connected to the lexical tree processors for storing processing results from the lexical tree processors and lexical tree identifiers to identify lexical trees to be processed by the lexical tree processors. A controller controls the lexical tree processors to process lexical trees identified in the results memory by performing parallel processing on a plurality of said lexical tree data structures.
1. A speech recognition circuit comprising:
one or more clusters of processors, each of the one or more clusters of processors comprising:
a plurality of processors; and
an acoustic model memory storing acoustic model data, wherein each of the plurality of processors is configured to compute a probability using the acoustic model data in the acoustic model memory, wherein:
the speech recognition circuit is configured to generate an initial score for an audio sample; and
the initial score is used to determine whether to continue processing to determine a final score via processing a larger amount of model data than that was processed to generate the initial score.
2. The speech recognition circuit of claim 1 , wherein the probability is an input to an evaluation of a state transition of a model of states.
3. The speech recognition circuit of claim 2 , wherein the model is a Hidden Markov Model.
4. The speech recognition circuit of claim 2 , wherein the probability is computed from a Gaussian mixture model and one or more feature vectors.
5. The speech recognition circuit of claim 1 , further comprising:
a buffer for storing one or more feature vectors coupled to at least one of the plurality of processors of the one or more clusters of processors.
6. The speech recognition circuit of claim 5 , further comprising:
a search controller coupled to the at least one of the plurality of processors of the one or more clusters of processors, the search controller capable of controlling the at least one of the plurality of processors of the one or more clusters of processors to initiate speech recognition processing in at least a subset of processors of the one or more clusters of processors.
7. The speech recognition circuit of claim 1 , wherein:
the one or more clusters of processors comprises a first cluster of processors and a second cluster of processors;
the first cluster comprises a first acoustic model memory; and
the second cluster comprises a second acoustic model memory that is distinct and separate from the first acoustic model memory.
8. The speech recognition circuit of claim 1 , wherein:
the one or more clusters of processors comprises a first cluster of processors; and
the first cluster comprises a first acoustic model coupled to all processors of the first cluster.