IP Library › Granted Patent US 10,854,466
Granted Patent B2
US 10,854,466 · App. 16/267,456 · Granted Dec 1, 2020

Etching method, method of manufacturing semiconductor chip, and method of manufacturing article

Inventors: Keiichiro Matsuo (Yokohama, JP); Susumu Obata (Yokohama, JP); Mitsuo Sano (Yokohama, JP); Kazuhito Higuchi (Yokohama, JP); Kazuo Shimokawa (Yokohama, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H01L21/3086H01L21/0332H01L21/0337H01L21/3081H01L21/76873
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Quick Facts
Patent No.
US 10,854,466
App. No.
16/267,456
Granted
Dec 1, 2020
Kind
B2
Abstract

An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.

Claims (28)

1. An etching method comprising:

forming an uneven structure including a projection on a surface of a semiconductor substrate;

forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and

supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst,

wherein the forming of the uneven structure includes:

forming a first mask layer having an opening on the surface;

etching the surface using the first mask layer as an etching mask; and

removing the first mask layer.

2. An etching method comprising:

forming an uneven structure including a projection on a surface of a semiconductor substrate:

forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and

supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst,

wherein the forming of the uneven structure includes:

forming a second mask layer having an opening on the surface; and

forming a semiconductor layer on the surface at the opening.

3. The etching method according to claim 2 , wherein the semiconductor layer is formed by epitaxial growth.

4. The etching method according to claim 1 , wherein the forming of the catalyst layer is performed in a presence of a third mask layer, the third mask layer opening at the projection and having a top surface that is flush with or higher than the top surface of the projection.

5. The etching method according to claim 4 , wherein the supplying of the etchant to the catalyst layer is performed with the third mask layer left on the semiconductor substrate.

6. The etching method according to claim 5 , wherein the third mask layer is more etching-resistant to the etchant than the projection.

7. The etching method according to claim 1 , wherein the etchant includes a corrosive agent and an oxidizer.

8. The etching method according to claim 7 , wherein the corrosive agent includes hydrofluoric acid, and the oxidizer includes at least one of hydrogen peroxide, nitric acid, AgNO 3 , KAuCl 4 , HAuCl 4 , K 2 PtCl 6 , H 2 PtCl 6 , Fe(NO 3 ) 3 , Ni(NO 3 ) 2 , Mg(NO 3 ) 2 , Na 2 S 2 O 8 , K 2 S 2 O 8 , KMnO 4 and K 2 Cr 2 O 7 .

9. The etching method according to claim 1 , wherein the projection has a height within a range of 0.15 μm to 0.5 μm.

10. The etching method according to claim 1 , wherein the noble metal is Au.

11. A method of manufacturing a semiconductor chip, comprising etching a semiconductor wafer by the etching method according to claim 1 to cingulate the semiconductor wafer into semiconductor chips, the surface being a surface of the semiconductor wafer.

12. A method of manufacturing an article, comprising etching the surface by the etching method according to claim 1 .

13. The etching method according to claim 1 , further comprising forming a third mask layer on the surface of the semiconductor substrate after forming the uneven structure and before forming the catalyst layer, the third mask layer opening at the projection, wherein among the top surface of the projection and the third mask layer, the catalyst layer is selectively formed at the top surface of the projection.

14. A method of manufacturing a semiconductor chip, comprising etching a semiconductor wafer by the etching method according to claim 2 to singulate the semiconductor wafer into semiconductor chips, the surface being a surface of the semiconductor wafer.

15. A method of manufacturing an article, comprising etching the surface by the etching method according to claim 2 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: MATSUO, KEIICHIRO; OBATA, SUSUMU; SANO, MITSUO; HIGUCHI, KAZUHITO; SHIMOKAWA, KAZUO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 048235/0693 →
Priority Claims (1)
JP 2018-021849 · Feb 9, 2018 · national
Continuity (1)
Related Publication 20190252199A1 · Aug 15, 2019