Signal receiving circuit and method, and signal detecting circuit

1. A system comprising:

a signal receiving circuit configured to receive an input voltage signal from an input terminal, the input voltage signal having a plurality of pulses according to a first input pattern or a second input pattern, the signal receiving circuit including:

an input voltage regulating circuit including an alternating current (AC) coupling circuit, a common-mode voltage generating circuit, and a feedback clamping circuit, the AC coupling circuit being connected to the input terminal, the AC coupling circuit configured to modify a waveform shape of the input voltage signal to obtain a regulated voltage signal, the common-mode voltage generating circuit including a first resistor, a second resistor, and a node disposed between the first resistor and the second resistor, the node being coupled to the AC coupling circuit, the feedback clamping circuit including a first current source, a second current source, and an inverter; and

a comparing circuit configured to compare the regulated voltage signal with a reference voltage signal, the comparing circuit configured to generate a comparison voltage signal in response to the comparison, the inverter configured to receive the comparison voltage signal,

the input voltage regulating circuit configured to adjust a current of the input voltage signal, in response to the comparison signal, to obtain the regulated voltage signal such that the comparison voltage signal has a pulse width that is substantially the same regardless of whether the input voltage signal includes the first input pattern or the second input pattern.

2. The system of claim 1 , wherein the signal receiving circuit is configured to identify whether the input voltage signal is a correct signal based on the comparison voltage signal.

3. The system of claim 1 , wherein the second input pattern has a high voltage value that is different from a high voltage value of the first input pattern, and the second input pattern has a low voltage value that is different from a low voltage value of the first input pattern.

4. The system of claim 1 , wherein the input terminal includes a common collector (CC) pin, the second input pattern having a high voltage different from a high voltage of the first input pattern, the second input pattern having a low voltage different from a low voltage of the first input pattern.

5. The system of claim 1 , wherein the regulated voltage signal includes a plurality of pulses, at least one of the plurality of pulses having a first edge and a second edge, wherein a magnitude of the first edge is different than a magnitude of the second edge.

6. The system of claim 1 , wherein the input voltage signal includes an analog voltage signal including at least one data signal or at least one clock signal.

7. The system of claim 1 , wherein the AC coupling circuit includes a capacitor having a first terminal and a second terminal, the first terminal being coupled to the input terminal, the second terminal being coupled to the node, the node being coupled to an input of the comparing circuit that receives the regulated voltage signal.

8. A system comprising:

a signal receiving circuit configured to receive an input voltage signal from an input terminal, the input voltage signal having a plurality of pulses according to a first input pattern or a second input pattern, the second input pattern being different than the first input pattern, the signal receiving circuit including:

an input voltage regulating circuit including an alternating circuit (AC) coupling circuit, a common-mode voltage generating circuit, and a feedback clamping circuit, the AC coupling circuit including a capacitor, the capacitor being connected to the input terminal, the AC coupling circuit configured to modify a waveform shape of the input voltage signal to obtain a regulated voltage signal, the common-mode voltage generating circuit configured to generate a substantially constant common mode voltage of the regulated voltage signal, the common-mode voltage generating circuit including a first resistor, a second resistor, and a node disposed between the first resistor and the second resistor, the node being coupled to the capacitor, the feedback clamping circuit including a first current source, a second current source, and an inverter; and

a comparing circuit configured to compare the regulated voltage signal with a reference voltage signal, the comparing circuit configured to generate a comparison voltage signal in response to the comparison, the inverter configured to receive the comparison voltage signal,

the input voltage regulating circuit configured to receive the comparison voltage signal, the input voltage regulating circuit configured to adjust a current of the input voltage signal, in response to the comparison voltage signal, to obtain the regulated voltage signal,

the comparison voltage signal defining a first pulse width in response to the input voltage signal having the first input pattern, the comparison voltage signal defining a second pulse width in response to the input voltage signal having the second input pattern the second pulse width being substantially the same as the first pulse width.

9. The system of claim 8 , wherein the feedback clamping circuit configured to receive the comparison voltage signal and clamp the regulated voltage signal based on the comparison voltage signal.

10. The system of claim 8 , wherein the signal receiving circuit is configured to identify whether the input voltage signal is a correct signal based on the comparison voltage signal.

11. The system of claim 8 , wherein the second input pattern has a high voltage value that is different from a high voltage value of the first input pattern, and the second input pattern has a low voltage value that is different from a low voltage value of the first input pattern.

12. The system of claim 8 , wherein the input terminal includes a common collector (CC) pin, the second input pattern having a high voltage different from a high voltage of the first input pattern, the second input pattern having a low voltage different from a low voltage of the first input pattern.

13. The system of claim 8 , wherein the regulated voltage signal includes a plurality of pulses, at least one of the plurality of pulses having a first edge and a second edge, wherein a magnitude of the first edge is different than a magnitude of the second edge.

14. The system of claim 8 , wherein the common-mode voltage generating circuit includes a first switch and a second switch, and the feedback clamping circuit includes a third switch and a fourth switch.

15. The system of claim 8 , wherein the capacitor has a first terminal coupled to the input terminal and a second terminal coupled to an input of the comparing circuit.

16. A method comprising:

receiving an analog voltage signal from an input terminal, the analog voltage signal including a first input pattern or a second input pattern, the second input pattern being different than the first input pattern;

modifying, by a capacitor and a common-mode voltage generating circuit, a waveform shape of the analog voltage signal to obtain a regulated voltage signal, the modifying including receiving a comparison voltage signal and adjusting a current of the analog voltage signal, in response to the comparison voltage signal, to obtain the regulated voltage signal, the common-mode voltage generating circuit including a first resistor, a second resistor, and a node disposed between the first resistor and the second resistor, the node being coupled to the capacitor;

clamping, by a feedback clamping circuit, the regulated voltage signal in response to the comparison voltage signal, the feedback clamping circuit including a first current source, a second current source, and an inverter, the inverter configured to receive the comparison voltage signal;

comparing the regulated voltage signal with a reference voltage signal; and

generating the comparison voltage signal in response to the comparison,

the comparison voltage signal defining a first pulse width in response to the input voltage signal having the first input pattern, the comparison voltage signal defining a second pulse width in response to the input voltage signal having the second input pattern, the second pulse width being substantially the same as the first pulse width.

17. The method of claim 16 , further comprising:

identifying whether the analog voltage signal is a correct signal based on the comparison voltage signal.

18. The system of claim 1 , wherein the common-mode voltage generating circuit is configured to generate a substantially constant common mode voltage of the regulated voltage signal regardless of whether the input voltage signal has the first input pattern or the second input pattern.

19. The system of claim 8 , wherein the common-mode voltage generating circuit is configured to generate the substantially constant common mode voltage regardless of whether the input voltage signal has the first input pattern or the second input pattern.