IP Library Granted Patent US 11,094,528
Granted Patent B2
US 11,094,528 · App. 16/282,909 · Granted Aug 17, 2021

Surface treatment of substrates using passivation layers

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Quick Facts
Patent No.
US 11,094,528
App. No.
16/282,909
Granted
Aug 17, 2021
Kind
B2
Abstract

Processes and apparatuses for the treatment of semiconductor workpieces are provided. In some embodiments, a method can include placing the workpiece in a processing chamber. The processing chamber can be separated from a plasma chamber by a separation grid assembly. The method can include forming a passivation layer on the workpiece in the processing chamber using radicals generated in a first plasma in the plasma chamber. The method can include performing a surface treatment process on the workpiece in the processing chamber using a second plasma generated in the plasma chamber.

Claims (23)

1. A method for processing a workpiece in a plasma processing apparatus, the plasma processing apparatus comprising a processing chamber separated from a plasma chamber by a separation grid assembly, the plasma processing apparatus comprising an inductively coupled plasma source operable to generate a plasma in the plasma chamber, the method comprising:

placing a workpiece on a substrate holder in the processing chamber, the workpiece comprising a semiconductor layer;

performing a passivation process with a first gas mixture in the plasma chamber to form a passivation layer on the workpiece; and

subsequent to performing the passivation process, performing a dry strip process with a second gas mixture in the plasma chamber to remove one or more materials from a surface of the workpiece with the passivation layer, wherein the passivation layer remains on the workpiece during the dry strip process;

wherein the dry strip process comprises injecting a cooling gas between a first grid plate and a second grid plate of the separation grid assembly into particles of the second gas mixture passing through the separation grid assembly;

wherein the first gas mixture comprises an inert gas and an N2 gas, wherein a flow rate of the inert gas relative to a flow rate of the N2 gas in the plasma chamber during the passivation process is less than about 20%;

wherein the second gas mixture comprises an H2 gas and an N2 gas.

2. The method of claim 1 , wherein the semiconductor layer comprises a SiGe layer.

3. The method of claim 2 , wherein the passivation layer is formed on the SiGe layer.

4. The method of claim 1 , wherein the passivation process comprises:

generating a first plasma with the first gas mixture in the plasma chamber;

passing radicals generated in the first plasma through the separation grid assembly; and

exposing a surface of the workpiece to radicals generated in the first plasma and passing through the separation grid assembly to form the passivation layer.

5. The method of claim 4 , wherein an RF source is energized with power in the range of about 2000 W to about 5000 W to generate the first plasma in the plasma chamber.

6. The method of claim 4 , wherein exposing a surface of the workpiece to radicals generated in the first plasma forms N or NH bonds on the workpiece.

7. The method of claim 1 wherein the inert gas comprises an Ar gas.

8. The method of claim 1 , wherein a pressure in the process chamber during passivation process is in the range of about 600 mT to about 1200 mT.

9. The method of claim 1 , wherein a temperature of the workpiece is maintained in a range of about 300° C. to about 400° C. during the passivation process.

10. The method of claim 1 , wherein the dry strip process comprises:

generating a second plasma in the second gas mixture in the plasma chamber;

passing radicals generated in the second plasma through the separation grid assembly; and

exposing a surface of the workpiece to radicals generated in the second plasma to conduct the dry strip process.

11. The method of claim 1 , wherein a ratio of the H2 gas to the N2 gas in the second gas mixture is in the range of about 0.2 to about 0.5.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2021
From: EAST WEST BANK
To: MATTSON TECHNOLOGY, INC.
Reel/Frame 055950/0452 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2019
From: MATTSON TECHNOLOGY, INC.
To: MATTSON TECHNOLOGY, INC.; BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY, CO., LTD
Reel/Frame 050582/0796 →
SECURITY INTEREST Recorded Sep 6, 2019
From: MATTSON TECHNOLOGY, INC.
To: EAST WEST BANK
Reel/Frame 050299/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2019
From: GAO, TONGCHUAN; KISHKO, GRIGORIY; VANIAPURA, VIJAY M.; YANG, MICHAEL X.
To: MATTSON TECHNOLOGY, INC.
Reel/Frame 048412/0573 →