IP Library › Granted Patent US 10,737,932
Granted Patent B2
US 10,737,932 · App. 16/284,735 · Granted Aug 11, 2020

Micro-electro-mechanical system structure and method for fabricating the same

Inventors: Yuan-Sheng Lin (Taoyuan, TW); Jung-Hao Chang (Taoyuan, TW); Chang-Sheng Hsu (Hsinchu, TW); Weng-Yi Chen (Hsinchu County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
B81B7/0061B81C1/00309B81B2201/0257B81B2203/0127B81B2203/0315B81C2201/0132B81C2201/0133
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Quick Facts
Patent No.
US 10,737,932
App. No.
16/284,735
Granted
Aug 11, 2020
Kind
B2
Abstract

A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.

Claims (42)

1. A micro-electro-mechanical system (MEMS) structure, comprising:

a substrate, having a through-hole;

a dielectric layer, disposed on the substrate and having a cavity in communication with the through-hole;

a membrane, having at least one vent hole, embedded in the dielectric layer, and together with the dielectric layer to define a first chamber that communicates with the through-hole;

a backplate, disposed on the dielectric layer; and

a blocking layer, made of a dielectric material other than that of the dielectric layer, wherein one end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.

2. The MEMS structure according to claim 1 , wherein the membrane is embedded in the dielectric layer, and the other end of the membrane extends into the cavity to divide the cavity into a first portion and a second portion; wherein the first portion communicates with the through-hole to form the first chamber, and the backplate together with the dielectric layer to define a second chamber comprising the second portion.

3. The MEMS structure according to claim 2 , wherein the another end of the membrane extends into the cavity extends into the first chamber or the second chamber.

4. The MEMS structure according to claim 2 , wherein the first chamber communicates with the second chamber through the at least one vent hole.

5. The MEMS structure according to claim 1 , wherein the blocking layer comprises silicon nitride (SiN) or polysilicon; the dielectric layer comprises silicon oxide (SiOx).

6. The MEMS structure according to claim 1 , wherein the at least one vent hole is a slit or a through-hole.

7. The MEMS structure according to claim 1 , wherein the blocking layer comprises a conductive material and the backplate comprises a conductive layer.

8. The MEMS structure according to claim 1 , wherein the blocking layer has a multilayer structure.

9. The MEMS structure according to claim 1 , wherein the backplate comprises at least one penetrating opening.

10. A method for fabricating a MEMS structure, comprising:

forming a dielectric layer on a substrate;

forming a membrane embedded in the dielectric layer, wherein the membrane has at least one vent hole;

forming a blocking layer made of a dielectric material other than that of the dielectric layer and embedded in the dielectric layer, wherein the blocking layer is disposed between the substrate and the membrane or disposed on one side of the membrane away from the substrate, is spatially isolated from the membrane and at least partially overlaps the vent hole;

forming a backplate on the dielectric layer, to make the backplate having at least one penetrating opening and exposing a portion of the dielectric layer;

forming a through-hole in the substrate to expose a portion of the dielectric layer; and

removing a portion of the dielectric layer from the through-hole, the at least one penetrating opening and the at least one vent hole to form a first chamber between the membrane and the substrate.

11. The method according to claim 10 , wherein the step of removing a portion of the dielectric layer from the through-hole comprises forming a second chamber between the substrate and the membrane, and the second chamber communicates the first chamber through the at least one vent hole.

12. The method according to claim 10 , wherein the step of forming the dielectric layer, the membrane and the blocking layer comprises:

forming a first SiOx layer on the substrate;

forming a patterned non-SiOx material layer on the first SiOx layer;

forming a second SiOx layer on the patterned non-SiOx material layer;

forming a patterned conductive film on the patterned non-SiOx material layer; and

forming a third SiOx layer on the patterned conductive film.

13. The method according to claim 12 , wherein the non-SiOx material layer comprises SiN or polysilicon.

14. The method according to claim 10 , wherein the step of forming the dielectric layer, the membrane and the blocking layer comprises:

forming a first SiOx layer on the substrate;

forming a patterned conductive film on the first SiOx layer;

forming a second SiOx layer on the patterned conductive film;

forming a patterned non-SiOx material layer on the second SiOx layer; and

forming a third SiOx layer on the patterned non-SiOx material layer.

15. The method according to claim 14 , wherein the non-SiOx material layer comprises SiN or polysilicon.

16. The method according to claim 10 , wherein the step for forming the backplate comprises:

forming a conductive layer on the dielectric layer;

forming a dielectric protection layer on the conductive layer; and

patterning the dielectric protection layer and the conductive layer.

17. The method according to claim 10 , wherein the step of removing a portion of the dielectric layer from the through-hole comprises a wet etching process.

18. The method according to claim 10 , wherein the step of forming the through-hole comprises a dry etching process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2019
From: LIN, YUAN-SHENG; CHANG, JUNG-HAO; HSU, CHANG-SHENG; CHEN, WENG-YI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 048428/0560 →
Priority Claims (1)
CN 2019 1 0031754 · Jan 14, 2019 · national
Continuity (1)
Related Publication 20200223687A1 · Jul 16, 2020
Cited By (2)
US 12,269,732 US 12,441,606